Texas Instruments TPS53622RSBT
- Part No.:
- TPS53622RSBT
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
TPS53622RSBT.pdf
- Description:
- IC REG CTRLR INTEL 2OUT 40WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,274
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Product details
Overview
TPS53622RSBT from Texas Instruments is a dual-channel VR13-compliant step-down multiphase controller supporting 1+1 or 2+0 phase configurations, featuring integrated NVM, PMBus™ telemetry, D-CAP+™ control with undershoot reduction (USR), and programmable loop compensation for server VCCIO/VMCP rails. It operates from 4.5 V to 17 V input, delivers dual outputs with 8-bit DAC (0.25–1.52 V or 0.5–2.8125 V), and supports dynamic phase shedding across –40°C to 125°C.
For engineers reviewing the TPS53622RSBT datasheet, TPS53622RSBT pinout, TPS53622RSBT application, or TPS53622RSBT equivalent, key selection criteria include VR13 SVID compliance, per-phase current reporting, PMBus-enabled telemetry (voltage/current/power/temperature/fault), driverless high-frequency operation, and AutoBalance™ phase balancing for high-density server power delivery.
Technical Context
The TPS53622RSBT implements D-CAP+™ architecture with adaptive transient response and undershoot reduction (USR), enabling fast load-step recovery with minimal output capacitance. Its dual-channel design supports independent voltage positioning, programmable slew rates via SVID or PMBus, and selectable 5 mV/10 mV DAC resolution per channel.
It integrates non-volatile memory (NVM) to store configuration defaults-including loop compensation, current limits, and phase shedding thresholds-reducing external component count. The device uses a 40-pin WQFN (RSB) package with exposed thermal pad and is fully compatible with TI NexFET™ power stages for high-efficiency, high-density solutions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 17 V - Supports wide-input server front-end supplies including 5 V, 12 V, and 15 V rails. |
| Output Voltage Range | 0.25 V–1.52 V or 0.5 V–2.8125 V - Dual-channel programmable range optimized for VR13 VCCIO and VMCP rails. |
| DAC Resolution | 8-bit with selectable 5 mV or 10 mV LSB - Enables precise digital voltage control and fine-grained VID steps per Intel VR13 spec. |
| Phase Configuration | Dual-channel: 1+1 or 2+0 phase - Flexible topology support for asymmetric or symmetric multi-rail processor power delivery. |
| Interface Protocol | PMBus v1.3 + SVID - Enables real-time telemetry reporting and dynamic voltage transitions in server management systems. |
| Operating Temperature | –40°C to 125°C - Rated for extended thermal environments in high-power server and storage applications. |
| Package Type | WQFN-40 (RSB), 5 mm × 5 mm, 0.8 mm max height - Thermally enhanced QFN with exposed pad for efficient heat dissipation. |
Pinout & Package
TPS53622RSBT is housed in a 40-pin thermally enhanced WQFN (RSB) package with 0.4 mm pitch, 5 mm × 5 mm body, and exposed thermal pad requiring PCB soldering for thermal and mechanical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1, VIN2 | Channel Input Supply | Independent input pins for each channel; support decoupling and current sensing per rail. |
| VOUT1, VOUT2 | Feedback Sense Inputs | High-impedance analog inputs for remote sensing of regulated output voltages. |
| PHASE1, PHASE2 | Gate Drive Outputs | Driverless outputs directly interface with NexFET™ power stages; no external gate drivers needed. |
| SCL, SDA | PMBus Interface | Standard I²C-compatible bus for telemetry readback and configuration programming. |
| SVID_DATA, SVID_CLK | Intel Serial VID Interface | Dedicated SVID lines for VR13-compliant communication with CPU host controller. |
| PGOOD1, PGOOD2 | Power-Good Status Outputs | Open-drain signals indicating valid regulation status per channel with adjustable delay. |
| EN1, EN2 | Channel Enable Inputs | Individual hardware enables for sequencing and fault isolation between dual rails. |
| EXPOSED PAD | Thermal & Ground Reference | Must be soldered to large PCB copper area for thermal conduction and low-impedance ground return. |
Key Features
| Feature | Design Value |
|---|---|
| AutoBalance™ Phase Balancing | Patented real-time current balancing across phases without external current-sense resistors or complex calibration. |
| Dynamic Phase Shedding | Programmable per-phase current threshold triggers automatic phase disable/enable to maximize efficiency at light and heavy loads. |
| Undershoot Reduction (USR) | Proprietary D-CAP+™ enhancement that detects rapid load increases and pre-charges output capacitors to suppress voltage dip. |
| NVM-Based Configuration Storage | Non-volatile memory retains all settings (compensation, limits, telemetry enable) across power cycles-eliminates boot-time reconfiguration. |
| Adjustable VCORE Slew Rate | Programmable dV/dt via SVID or PMBus allows controlled voltage transitions during frequency scaling or power-state changes. |
Applications
| Server VCCIO Power Delivery | VR13 VMCP Rail Regulation |
|---|---|
|
Use Scenario: Delivering stable, dynamically scaled 1.05 V–1.2 V power to CPU I/O buffers in dual-socket x86 servers. IC Role / Device Role / Timing Role: Dual-channel VR13-compliant controller managing independent VCCIO rails with SVID handshake and PMBus telemetry. Use Value: Enables precise voltage positioning, real-time current monitoring per rail, and seamless integration with BMC-based power management firmware. |
Use Scenario: Providing tightly regulated 0.9 V–1.1 V supply to memory controller power domains in high-bandwidth DDR4/DDR5 systems. IC Role / Device Role / Timing Role: Second-channel controller operating in parallel with VCCIO rail, supporting independent loop tuning and phase shedding. Use Value: Reduces system-level ripple and improves transient response margin for memory subsystems under bursty traffic loads. |
| ASIC Dual-Rail Power System | High-Density Compute Module |
|
Use Scenario: Powering heterogeneous ASICs requiring separate core and I/O voltage domains with tight sequencing and telemetry. IC Role / Device Role / Timing Role: Dual-output controller delivering independent, digitally programmable rails with synchronized startup and fault reporting. Use Value: Eliminates need for discrete supervisors or sequencers; simplifies BOM while enabling per-rail diagnostics via PMBus. |
Use Scenario: Compact 1U server or AI accelerator module where board space and thermal density constrain power solution size. IC Role / Device Role / Timing Role: Driverless controller paired with TI NexFET™ power stages to achieve >90% peak efficiency in <10 cm² footprint. Use Value: Enables high-frequency switching (>1 MHz) with minimal external components and direct thermal path via exposed pad. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multiphase VR13 controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS53632RSBT | Single-channel VR13 controller with identical NVM/PMBus features but no dual-rail capability; lacks second VOUT/SVID channel. | Used when only one VR13 rail is required (e.g., single-rail CPU core), reducing cost and complexity versus dual-channel TPS53622RSBT. | Select TPS53632RSBT if system requires only one regulated rail and space/cost constraints favor single-channel integration. |
| ISL6381IRZ | VR12.5/VR13-compatible dual-channel controller with PWM (not D-CAP+) architecture; no USR or AutoBalance™; requires external gate drivers. | Supports legacy VR12.5 platforms and offers higher flexibility in loop compensation but lacks integrated telemetry and driverless operation. | Choose ISL6381IRZ for designs needing backward compatibility with VR12.5 BIOS or requiring analog loop tuning over digital configurability. |
Compared with TPS53622RSBT, TPS53632RSBT reduces feature set to single-rail operation while maintaining VR13 compliance and telemetry, whereas ISL6381IRZ provides analog control flexibility and VR12.5 support but requires more external components and lacks USR/AutoBalance™ efficiency enhancements.
Availability
TPS53622RSBT is available at Aetrix Electronics and suitable for server motherboard design, high-performance computing power modules, and VR13-compliant ASIC power systems requiring stable component supply, full PMBus telemetry, and dual-rail digital control.
Supply support for TPS53622RSBT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power conversion ICs.
The TPS53622RSBT belongs to TI's VR13-compliant multiphase controller product line, engineered specifically for next-generation server and data center applications demanding digital telemetry, dynamic efficiency optimization, and compact high-current power delivery.
FAQ
What is the primary function of the TPS53622RSBT in a server power architecture?
The TPS53622RSBT serves as a dual-channel VR13-compliant step-down multiphase controller, managing two independent power rails-typically VCCIO and VMCP-for modern x86 processors. It executes real-time voltage regulation using D-CAP+™ control, supports SVID and PMBus interfaces, and enables dynamic phase shedding and AutoBalance™ current sharing. Its role is central to achieving high efficiency, fast transient response, and full telemetry visibility in server motherboard power delivery networks.
Does the TPS53622RSBT require external gate drivers when used with TI NexFET™ power stages?
No, the TPS53622RSBT does not require external gate drivers when interfacing with TI NexFET™ power stages. It features driverless gate drive outputs (PHASE1 and PHASE2) designed to directly drive high-side and low-side FETs in synchronous buck topologies. This eliminates gate driver ICs, reduces component count, and minimizes propagation delay-enabling higher switching frequencies and improved efficiency in dense server power designs.
How does the TPS53622RSBT implement undershoot reduction (USR) during load transients?
The TPS53622RSBT implements undershoot reduction (USR) through its proprietary D-CAP+™ control architecture, which continuously monitors output voltage slope and load current rate-of-change. Upon detecting a rapid load increase, it preemptively extends high-side FET on-time and adjusts pulse width before significant voltage droop occurs. This predictive action-enabled by internal current estimation and adaptive loop response-suppresses undershoot without relying on large bulk capacitance, improving transient performance in VR13 applications.
Can the TPS53622RSBT store configuration settings permanently without external memory?
Yes, the TPS53622RSBT integrates non-volatile memory (NVM) capable of storing all user-programmed parameters-including loop compensation coefficients, per-phase current limits, phase shedding thresholds, voltage positioning offsets, and PMBus telemetry enable states. These settings persist across power cycles and eliminate the need for external EEPROM or configuration firmware, simplifying system initialization and reducing BOM cost and board area.
What thermal management requirements apply to the TPS53622RSBT's exposed pad?
The TPS53622RSBT's exposed thermal pad (Pin 41) must be soldered to a dedicated PCB copper pour connected to internal or external ground planes for effective thermal conduction. TI recommends a minimum 75% solder coverage area under the pad, use of thermal vias (filled or tented), and adherence to the land pattern and stencil design guidelines in SLUA271. Failure to properly thermally attach the pad risks exceeding junction temperature limits and degrading long-term reliability in continuous high-load operation.
TPS53622RSBT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP+™
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Controller, Intel VR13
- Voltage - Input:
- 4.5V ~ 17V
- Number of Outputs:
- 2
- Voltage - Output:
- 0.25V ~ 1.52V, 0.5V ~ 2.8125V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-WQFN (5x5)
TPS53622RSBT FAQ
1.How can I place an order for TPS53622RSBT through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS53622RSBT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS53622RSBT reliable?
The price and inventory of TPS53622RSBT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS53622RSBT is usually 5 days.
3.What payment methods are accepted for TPS53622RSBT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS53622RSBT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS53622RSBT?
TPS53622RSBT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS53622RSBT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS53622RSBT?
For technical support, including TPS53622RSBT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS53622RSBT requirements.
6.How does Aetrix verify that TPS53622RSBT is sourced from the original manufacturer or authorized distributors?
All TPS53622RSBT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS53622RSBT meets industry standards.
7.What is the process for return or replacement of TPS53622RSBT?
All TPS53622RSBT units undergo pre-shipment inspection (PSI). If there is an issue with TPS53622RSBT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS53622RSBT part is unused and in its original packaging.
Return procedure for TPS53622RSBT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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