Texas Instruments TPS536C9TRSLR
- Part No.:
- TPS536C9TRSLR
- Manufacturer:
- Texas Instruments
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
TPS536C9TRSLR.pdf
- Description:
- IC REG BUCK ADJ 765A DL 48VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,000
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Product details
Overview
TPS536C9TRSLR from Texas Instruments is a dual-channel, 12-phase VR14 SVID-compliant step-down controller with TLVR topology support, D-CAP+™ control architecture, PMBus® v1.3.1 interface, and integrated non-volatile memory (NVM). It delivers 0.25V–5.5V output across two configurable channels (N+M ≤ 12), supports TI smart power stages, and enables dynamic phase shedding for data center server VR applications.
For engineers reviewing the TPS536C9TRSLR datasheet, TPS536C9TRSLR pinout, TPS536C9TRSLR application, or TPS536C9TRSLR equivalent, key selection considerations include VR14 SVID compliance with PSYS, programmable per-phase valley current limit, diode braking with timeout, NVM-based configuration storage, and 48-pin VQFN (RSL) thermal-pad package for high-density multiphase designs.
Technical Context
The TPS536C9TRSLR implements a dual-output D-CAP+™ control architecture optimized for fast transient response and precise dynamic current sharing across up to 12 interleaved phases. Its TLVR support enables low-ESR output capacitor usage while maintaining stability under rapid load steps.
It integrates VR14 SVID with PSYS reporting, backward compatibility to VR13.HC/VR13.0, and full PMBus® v1.3.1 telemetry for voltage, current, power, temperature, and fault status - all configurable and stored in on-chip NVM without external EEPROM.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5V to 17V - supports wide-input 12V/5V intermediate bus architectures common in server VRMs. |
| Output Voltage Range | 0.25V to 5.5V - covers CPU core, SoC, ASIC, and I/O rail requirements with fine-grained SVID control. |
| Max Phase Count | 12 phases (N+M ≤ 12, M ≤ 6) - enables high-current delivery (>300A) with thermal and layout scalability. |
| Control Architecture | D-CAP+™ - provides zero-latency transient response and eliminates need for external compensation components. |
| Interface Standard | VR14 SVID + PMBus® v1.3.1 - enables host-controlled adaptive voltage positioning (AVP), telemetry logging, and fault diagnostics. |
| Package | VQFN-48 (RSL), 6.00mm × 6.00mm - exposes thermal pad for efficient heat dissipation in high-power density server PCBs. |
| Operating Temperature | –40°C to +125°C - qualified for enterprise server ambient and junction conditions per JEDEC JESD22-A108. |
Pinout & Package
VQFN-48 (RSL) package with 6.00mm × 6.00mm footprint, 0.4mm pitch, and exposed thermal pad (Pin 49) requiring solder connection to PCB ground plane for thermal and mechanical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PIN 1 (Index) | Phase 1 PWM output | Drives high-side FET of first phase; synchronized timing reference for interleaved operation. |
| PIN 13–24 | Phase 2–12 PWM outputs | Twelve dedicated PWM outputs supporting N+M channel assignment and automatic phase shedding. |
| PIN 25–36 | IMON current-sense inputs | Accepts analog current monitor signals from TI smart power stages with internal 1kΩ termination. |
| PIN 37–40 | SVID bus (SCLK, SDATA, ALERT#, PSYS) | Intel VR14-compliant bidirectional interface for AVP, margining, and system-level power state coordination. |
| PIN 41–44 | PMBus® (CLK, DATA, ALERT#, VDDIO) | Full PMBus® v1.3.1 interface enabling read/write access to telemetry, configuration, and NVM registers. |
| PIN 49 (Thermal Pad) | Ground / Thermal Plane | Must be soldered to large PCB copper area for thermal conduction and EMI reduction; electrically connected to GND. |
Key Features
| Feature | Design Value |
|---|---|
| TLVR topology support | Enables use of low-DCR inductors and reduced output capacitance while maintaining loop stability under fast load transients. |
| Per-phase valley current limit (OCL) | Programmable via PMBus® to prevent phase overload during asymmetric current distribution or fault conditions. |
| Diode braking with programmable timeout | Reduces output voltage overshoot during sudden load release by activating synchronous rectifier as freewheeling diode for defined duration. |
| Automatic NVM fault logging | Stores last 8 fault events (OVP, UVP, OT, phase loss) with timestamps and register snapshots for post-fault root-cause analysis. |
| Multi-slope IMON calibration | Compensates for gain nonlinearity across current range, improving system-level current reporting accuracy to ±1.5% over temperature. |
Applications
| Data Center Rack Server VRM | Hardware Accelerator Power Delivery |
|---|---|
Use Scenario: High-current, multi-rail power delivery for dual-socket Xeon Scalable processors and memory subsystems in 1U/2U rack servers. IC Role / Device Role / Timing Role: Primary VR14-compliant multiphase controller managing up to 12 phases across CPU core, GT, and VCCIO rails with PSYS coordination. Use Value: Delivers <300A total output with <1% load-line deviation and <50mV transient undershoot/overshoot under 50A/µs load steps. | Use Scenario: Power management for FPGA-based AI accelerators (e.g., Xilinx Alveo, NVIDIA A100 GPU companion modules) requiring tight voltage regulation and telemetry. IC Role / Device Role / Timing Role: Dual-channel controller independently regulating core logic (0.75V) and HBM2E interface (1.2V) rails with synchronized phase interleaving. Use Value: Enables real-time current/power telemetry via PMBus® for thermal-aware workload scheduling and dynamic power capping. |
| Network Interface Card (NIC) VR | ASIC-Based Edge Compute Platform |
Use Scenario: Compact, high-efficiency VR for 100G/200G SmartNICs with integrated ARM cores and packet processing engines. IC Role / Device Role / Timing Role: Single-channel 6-phase configuration delivering 0.8V @ 80A to network processor, leveraging D-CAP+™ for sub-100ns transient response. Use Value: Eliminates external compensation network and reduces BOM count by 4 components per rail versus traditional PID controllers. | Use Scenario: Power solution for custom ASICs in edge inference appliances requiring multiple precision rails (e.g., 0.65V core, 1.8V I/O, 3.3V aux). IC Role / Device Role / Timing Role: Configurable dual-output controller with independent NVM profiles for each rail, supporting staggered startup and adaptive voltage positioning. Use Value: Achieves <±0.5% output accuracy over line/load/temperature using per-rail IMON calibration and SVID margining. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multiphase VR controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL91302BIRZ-T7A | Single-channel, max 8-phase, no VR14 SVID; uses proprietary digital interface instead of PMBus®/SVID. | Lacks PSYS support and VR14 compliance; suitable only for non-Intel platforms with simpler telemetry needs. | Select when VR14/SVID is not required and lower phase count suffices for mid-tier compute. |
| MP2960GQ-Z | 12-phase, VR14.0 compliant but lacks TLVR support, NVM fault logging, and diode braking; uses analog voltage mode control. | Higher output capacitance needed; no built-in soft-shutdown for OVP; limited telemetry granularity vs. PMBus® v1.3.1. | Choose for cost-sensitive VR14 systems where D-CAP+™ transient performance and advanced protection are secondary. |
Compared with ISL91302BIRZ-T7A and MP2960GQ-Z, the TPS536C9TRSLR uniquely combines VR14 PSYS, TLVR topology enablement, and NVM-based fault logging - making it the only option among the three qualified for high-reliability data center CPU VRMs requiring Intel specification compliance and field-diagnostic capability.
Availability
TPS536C9TRSLR is available at Aetrix Electronics and suitable for data center rack servers, hardware accelerator modules, and high-performance NICs requiring stable component supply, long-term lifecycle support, and traceable sourcing for production programs.
Supply support for TPS536C9TRSLR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and power management ICs for industrial, automotive, and computing markets.
The TPS536C9TRSLR belongs to TI's high-performance VR controller product line, designed specifically for next-generation server and AI accelerator power delivery systems demanding VR14 compliance, ultra-fast transient response, and intelligent telemetry-driven power management.
FAQ
What is the maximum supported phase count for the TPS536C9TRSLR?
The TPS536C9TRSLR supports up to 12 total phases across its dual-channel architecture, with N+M ≤ 12 and M ≤ 6. This allows flexible allocation - for example, 8 phases on Channel A and 4 on Channel B - enabling scalable current delivery for heterogeneous loads like CPU cores and I/O domains. The phase count is configured via NVM settings and verified through PMBus® register reads.
Does the TPS536C9TRSLR support TLVR topology out of the box?
Yes, the TPS536C9TRSLR natively supports Trans-Inductor Voltage Regulator (TLVR) topology through dedicated control loop enhancements and programmable parameters accessible via PMBus®. TLVR mode reduces output capacitor count and improves transient response by leveraging coupled inductors and active current balancing - confirmed in TI's SLUSFF0A datasheet Section 8.3.3.
How does the TPS536C9TRSLR handle overvoltage faults?
The TPS536C9TRSLR implements a new soft-shutdown option for overvoltage faults, introduced in the July 2025 revision of the datasheet. Upon OVP detection, it gradually ramps down PWM duty cycles rather than hard-shutting off - minimizing system stress and preventing secondary voltage spikes. This behavior is configurable via PMBus® command and stored in NVM.
Can the TPS536C9TRSLR operate without external EEPROM?
Yes, the TPS536C9TRSLR includes on-chip non-volatile memory (NVM) that stores all configuration parameters - including phase mapping, current limits, telemetry scaling, and SVID settings - eliminating the need for external EEPROM. Default values are factory-programmed, and user updates persist across power cycles without additional components.
What is the thermal pad (Pin 49) connection requirement for the TPS536C9TRSLR?
The exposed thermal pad (Pin 49) of the TPS536C9TRSLR must be soldered to a dedicated PCB ground plane with ≥71% solder paste coverage, as specified in TI's SLUA271 layout guidelines. This connection is mandatory for thermal dissipation (enabling 125°C operation) and mechanical reliability - floating or unconnected pads cause thermal shutdown and premature failure.
TPS536C9TRSLR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP+™
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 17V
- Voltage - Output (Min/Fixed):
- 0.25V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 765A
- Frequency - Switching:
- -
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-VQFN (6x6)
TPS536C9TRSLR FAQ
1.How can I place an order for TPS536C9TRSLR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS536C9TRSLR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS536C9TRSLR reliable?
The price and inventory of TPS536C9TRSLR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS536C9TRSLR is usually 5 days.
3.What payment methods are accepted for TPS536C9TRSLR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS536C9TRSLR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS536C9TRSLR?
TPS536C9TRSLR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS536C9TRSLR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS536C9TRSLR?
For technical support, including TPS536C9TRSLR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS536C9TRSLR requirements.
6.How does Aetrix verify that TPS536C9TRSLR is sourced from the original manufacturer or authorized distributors?
All TPS536C9TRSLR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS536C9TRSLR meets industry standards.
7.What is the process for return or replacement of TPS536C9TRSLR?
All TPS536C9TRSLR units undergo pre-shipment inspection (PSI). If there is an issue with TPS536C9TRSLR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS536C9TRSLR part is unused and in its original packaging.
Return procedure for TPS536C9TRSLR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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