Texas Instruments TPS54061QDRBRQ1

Overview

TPS54061QDRBRQ1 from Texas Instruments is a 60-V, 200-mA automotive-grade synchronous step-down DC–DC converter with integrated high-side (1.5 Ω) and low-side (0.8 Ω) MOSFETs, 90 µA non-switching quiescent current, and adjustable 50 kHz–1.1 MHz switching frequency. It delivers regulated bias power in vehicle infotainment head units requiring wide-input, low-I_Q operation.

For engineers reviewing the TPS54061QDRBRQ1 datasheet, TPS54061QDRBRQ1 pinout, TPS54061QDRBRQ1 application, or TPS54061QDRBRQ1 equivalent, key selection considerations include its AEC-Q100 Grade 1 qualification (–40°C to 125°C ambient), diode-emulation light-load efficiency mode, 0.8 V ±1% reference accuracy, and RT/CLK pin synchronization capability for EMI-sensitive automotive subsystems.

Technical Context

This device implements peak-current-mode control with internal slope compensation to prevent subharmonic oscillation and supports cycle-by-cycle current limiting with a 250–500 mA high-side current-limit threshold. Its error amplifier features 108 µA/V transconductance and programmable slow-start via a digital DAC-based ramp over 1114 switching cycles.

The RT/CLK pin operates in dual mode: as a resistor-set oscillator (50–1100 kHz) or as a high-impedance PLL input synchronized to external clocks (300–1100 kHz), with automatic fallback to resistor mode if clock stops. Thermal shutdown activates at 176°C, and internal overvoltage protection disables the high-side switch when output exceeds 109% of nominal.

Key Specifications

Pinout & Package

TPS54061QDRBRQ1 uses an 8-pin SON (DRB) package with an exposed thermal pad (Pin 9) that must be soldered to GND on the PCB for thermal and electrical integrity. The package measures 3.00 mm × 3.00 mm with 0.65 mm pitch.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck regulator applications.

Compared with LM5164QDDARQ1 and TPS54361QDPRRQ1, the TPS54061QDRBRQ1 offers the smallest footprint (3 mm × 3 mm), lowest operating IQ (90 µA), and fully integrated dual-FET architecture - making it optimal for space-constrained, ultra-low-power automotive subsystems where 200 mA is sufficient.

Availability

TPS54061QDRBRQ1 is available at Aetrix Electronics and suitable for automotive infotainment, ADAS camera modules, telematics control units, and body control subsystems requiring stable component supply with AEC-Q100 compliance and long-term production support.

Supply support for TPS54061QDRBRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader designing analog ICs, embedded processors, and system solutions for automotive, industrial, and communications markets.

The TPS54061-Q1 belongs to TI's automotive-qualified DC–DC converter product line, engineered specifically for reliable, low-quiescent-power bias supply generation in safety-critical vehicle subsystems operating across extended temperature ranges.

FAQ

What is the minimum controllable on-time of the TPS54061QDRBRQ1, and how does it affect high-input-voltage operation?

The TPS54061QDRBRQ1 has a minimum controllable on-time of 120 ns. At high input voltages (e.g., 60 V) and low output voltages (e.g., 3.3 V), this limits the maximum achievable switching frequency to avoid duty-cycle violation. For example, at VIN = 60 V and VOUT = 3.3 V, the theoretical minimum frequency is ~240 kHz. The device mitigates this via frequency shift - dividing the switching frequency by up to 8 during overload to maintain control. This behavior is documented in the TPS54061QDRBRQ1 datasheet Section 7.3.9.

Can the TPS54061QDRBRQ1 operate with ceramic output capacitors, and what is the recommended ESR range?

Yes, the TPS54061QDRBRQ1 is explicitly designed for stability with ceramic output capacitors and has no minimum ESR requirement. TI recommends using X5R or X7R dielectrics with typical values of 10–47 µF. The error amplifier compensation network (connected to COMP) is optimized for low-ESR ceramics, eliminating the need for bulk aluminum electrolytics. This is confirmed in the TPS54061QDRBRQ1 datasheet Features list and Section 8.2.1.

How is the undervoltage lockout (UVLO) threshold adjusted using the EN pin on the TPS54061QDRBRQ1?

The EN pin of the TPS54061QDRBRQ1 has an internal 1.2 µA pullup current source. To raise the UVLO threshold above the default 4.5 V, connect two resistors: R_UVLO1 from VIN to EN, and R_UVLO2 from EN to GND. Using Equation 2 from the TPS54061QDRBRQ1 datasheet, R_UVLO1 = (V_{UVLO_START} − 1.23 V) / 1.2 µA − R_UVLO2. Hysteresis is provided by a 3.5 µA current sink when EN falls below 1.18 V.

Does the TPS54061QDRBRQ1 support external clock synchronization, and what are the timing requirements?

Yes, the TPS54061QDRBRQ1 supports external clock synchronization via the RT/CLK pin. The external clock must have amplitude exceeding 0.5 V (low) and 1.8 V (high), with pulse widths ≥40 ns. Synchronization range is 300–1100 kHz. The PH rising edge aligns to the falling edge of the RT/CLK signal. PLL lock-in occurs within 100 µs. These specifications are detailed in TPS54061QDRBRQ1 datasheet Sections 6.5 and 7.3.10.

What thermal performance can be expected from the TPS54061QDRBRQ1 in a standard 2-layer PCB layout?

In a standard 2-layer PCB with 1-in² 2-oz copper thermal pad connected to GND, the TPS54061QDRBRQ1 achieves R_θJB = 18.1°C/W (junction-to-board). At 200 mA output and 12 V input, typical power dissipation is ~180 mW, resulting in ~3.3°C junction-to-board temperature rise above ambient. Full thermal data, including R_θJA = 42.9°C/W and ψ_JB = 18.3°C/W, is provided in TPS54061QDRBRQ1 datasheet Section 6.4.