Texas Instruments TPS54218RTET
- Part No.:
- TPS54218RTET
- Manufacturer:
- Texas Instruments
- Package:
- 16-WFQFN Exposed Pad
- Datasheet:
-
TPS54218RTET.pdf
- Description:
- IC REG BUCK ADJ 2A 16WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,660
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS54218RTET from Texas Instruments is a 2.95-V to 6-V input, 2-A synchronous step-down DC/DC converter with integrated 30-mΩ high- and low-side MOSFETs, 2-MHz maximum switching frequency, ±1% voltage reference accuracy over –40°C to 150°C, and power-good monitoring for industrial power rails in factory automation and wireless infrastructure systems.
For engineers reviewing the TPS54218RTET datasheet, TPS54218RTET pinout, TPS54218RTET application, or TPS54218RTET equivalent, key selection considerations include its WQFN-16 thermal-pad package, RT/CLK synchronization capability, adjustable soft-start via external capacitor, UVLO programmability on EN, and 350-μA quiescent current at full load.
Technical Context
The TPS54218RTET implements peak-current-mode control with internal slope compensation to prevent subharmonic oscillation across 0–100% duty cycle. Its constant-frequency PWM architecture supports external synchronization via RT/CLK pin and enables stable regulation using only a single feedback resistor divider on VSENSE.
It integrates boot recharge circuitry and monitors BOOT-PH voltage with UVLO (2.1 V threshold) to sustain high-side conduction; the COMP pin serves as error amplifier output and current comparator input, with clamped min/max voltages for transient response and overload protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.95 V to 6 V - supports single 3.3-V or 5-V rail, compatible with USB PD and industrial 5-V supplies. |
| Output Current | 2 A continuous - sufficient for FPGA core rails, DSP I/O, or microcontroller subsystems without external heatsinking. |
| Switching Frequency | 200 kHz to 2 MHz - adjustable via RT resistor or external clock; enables compact 1-μH inductors at 2 MHz. |
| Voltage Reference | 0.803 V ±1% over temperature - ensures ±18 mV absolute output tolerance at 1.8 V setting, critical for low-voltage logic. |
| Quiescent Current | 350 μA typical - minimizes no-load power loss in always-on subsystems like sensor hubs or remote monitoring nodes. |
| Shutdown Current | 2 μA - enables battery-backed retention during deep sleep in portable or energy-harvesting applications. |
| Thermal Package | 3-mm × 3-mm WQFN-16 with PowerPad - achieves 37°C/W θJA on JEDEC 4-layer board, supporting 2-A operation at 70°C ambient. |
Pinout & Package
TPS54218RTET uses a thermally enhanced 3-mm × 3-mm, 16-pin WQFN package with exposed PowerPad (GND-connected) for optimal thermal dissipation. Pin numbering follows top-view layout with Pin 1 at top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN | Enable control input | Pull below 1.2 V to disable; internal pullup allows floating = enabled; UVLO threshold adjustable with resistor divider. |
| PH | Power switch node | Drain of low-side MOSFET / source of high-side MOSFET; connects to inductor and BOOT capacitor. |
| VSENSE | Feedback input | Inverting input of transconductance error amplifier; sets output voltage via resistor divider to 0.803 V reference. |
| PWRGD | Open-drain power-good | Asserts low when VOUT falls outside 93–107% of nominal; requires external pullup for system sequencing or fault signaling. |
| RT/CLK | Timing/sync interface | Resistor-to-GND sets fSW (200–2000 kHz); accepts external clock (300–2000 kHz) with PLL lock-in time ≤14 μs. |
| COMP | Error amplifier output | Drives current comparator; connects to RC compensation network for loop stability across load/transient conditions. |
| VOUT | Regulated output | Not a pin - derived at PH node; output voltage set by VSENSE divider; supports down to 0.803 V minimum. |
| BOOT | High-side gate drive | Requires 0.1-μF X7R/X5R ceramic between BOOT and PH; UVLO disables high-side if BOOT-PH < 2.1 V. |
| VIN | Main input supply | Dual VIN pins (1 & 2) reduce trace inductance; accepts 2.95–6 V; internal UVLO triggers at 2.6 V (rising). |
| SS | Soft-start control | Capacitor-based ramp; 2.07-μA charge current enables precise startup timing and pre-bias safe start-up. |
| AGND | Analog ground | Must be tied to GND near device; separates noise-sensitive analog circuitry from power ground return paths. |
| GND | Power ground | Direct connection to PowerPad; multiple vias required under exposed pad for thermal and EMI performance. |
| PowerPad | Thermal & electrical GND | Exposed copper pad (Pin 16); must be soldered to PCB ground plane with ≥4 thermal vias for RθJB = 23.1°C/W. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated dual MOSFETs | 30-mΩ high- and low-side RDS(on) enable >90% efficiency at 2 A/1.8 V out with minimal external components. |
| Programmable soft-start | External SS capacitor controls monotonic VOUT ramp; prevents inrush current and enables controlled power sequencing. |
| Synchronization capability | RT/CLK pin accepts external clock (300–2000 kHz) with PLL lock; eliminates beat frequencies in multi-rail systems. |
| Pre-bias safe start-up | Starts into precharged output without reverse current flow - essential for hot-swap and redundant power architectures. |
| Comprehensive protection | Cycle-by-cycle current limit, thermal shutdown (175°C), frequency foldback, and UV/OV PWRGD detection ensure robust field operation. |
Applications
| Factory Automation PLC I/O Module | Broadband Fixed-Line Access DSLAM |
|---|---|
Use Scenario: Powers isolated 3.3-V and 1.8-V digital I/O banks in modular PLC backplanes with strict EMC and thermal constraints. IC Role / Device Role / Timing Role: Primary point-of-load regulator delivering clean, sequenced 2-A rails to FPGA configuration logic and communication peripherals. Use Value: 2-MHz switching enables <1-μH inductors, reducing board area by 40% vs. 500-kHz alternatives while maintaining >92% efficiency. |
Use Scenario: Supplies 1.2-V core and 1.8-V I/O rails to multi-port DSL PHY chips in space-constrained DSLAM line cards. IC Role / Device Role / Timing Role: Synchronous buck converter with RT/CLK sync to system master clock, eliminating switching noise coupling into analog front-end. Use Value: ±1% VREF and 350-μA IQ ensure stable low-noise supply under dynamic line-card loading, extending mean time between failures. |
| Wireless Infrastructure Remote Radio Unit | Industrial Embedded Vision Sensor Node |
Use Scenario: Powers RF transceiver ASIC and ADC/DAC in outdoor RRUs operating from -40°C to +85°C ambient. IC Role / Device Role / Timing Role: High-reliability DC/DC with thermal shutdown (175°C) and wide-junction-temp support (–40°C to 150°C). Use Value: WQFN PowerPad and 37°C/W θJA allow full 2-A output without heatsink in sealed enclosures with limited airflow. |
Use Scenario: Powers image sensor, ISP processor, and LPDDR interface in battery-assisted edge vision nodes requiring ultra-low standby power. IC Role / Device Role / Timing Role: Efficient buck converter with 2-μA shutdown current and programmable EN threshold for wake-on-event functionality. Use Value: Safe start-up into prebiased output prevents bus contention during cold-boot of multi-sensor clusters sharing common power domain. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54228RTET | Same 2-A rating and WQFN-16 package but adds D-CAP2 control mode and higher 2.2-MHz max fSW; 400-μA IQ. | Better transient response for fast-digital loads (e.g., SoCs), but less suitable for noise-sensitive RF applications due to variable-frequency operation. | Select TPS54228RTET when load step response dominates over EMI concerns; retain TPS54218RTET for fixed-frequency, clock-synchronized designs. |
| MP2315DJ-LF-Z | 2-A, 6-V input, but uses current-mode control without RT/CLK sync; 350-μA IQ; smaller 2-mm × 2-mm TSOT23-8 package. | Limited to 1.5-MHz max fSW and lacks PWRGD or soft-start adjustability; suited for cost-sensitive, space-constrained consumer modules. | Choose MP2315DJ-LF-Z for footprint-limited applications where sequencing and system-level fault reporting are not required. |
Compared with TPS54218RTET, TPS54228RTET offers faster transient recovery at the expense of deterministic EMI profile, while MP2315DJ-LF-Z trades feature completeness for size and BOM cost-making TPS54218RTET the balanced choice for industrial timing-critical designs.
Availability
TPS54218RTET is available at Aetrix Electronics and suitable for factory automation PLCs, broadband DSLAM line cards, wireless infrastructure RRUs, and industrial embedded vision nodes requiring stable component supply across extended temperature and long production lifecycles.
Supply support for TPS54218RTET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-reliability power conversion solutions.
The TPS54218RTET belongs to TI's SWIFT™ synchronous buck converter family, designed specifically for space-constrained, thermally demanding industrial and communications equipment requiring precision regulation and robust fault handling.
FAQ
What is the recommended inductor value for TPS54218RTET at 1.8-V output and 2-MHz switching?
For TPS54218RTET operating at 2 MHz and 1.8-V output, a 0.47-μH to 1.0-μH shielded power inductor with ≥3-A saturation current is recommended. At 2 MHz, 0.68-μH provides optimal balance of ripple current (<30% of 2-A load), core loss, and physical size. TI's WEBENCH® Power Designer confirms 0.68-μH yields 1.2-A peak inductor current and <15-mV output ripple with standard 22-μF output capacitance.
Does TPS54218RTET support output voltages below 0.8 V?
No, TPS54218RTET does not support output voltages below its internal 0.803-V reference voltage. The VSENSE pin is internally biased to this reference, and the feedback divider ratio determines VOUT = 0.803 V × (1 + R1/R2). Minimum practical output is therefore 0.803 V, achievable with R2 = ∞ (i.e., no R2) and R1 = 0 - though layout parasitics and noise make sub-0.85-V designs impractical without external amplification.
How is the soft-start time calculated for TPS54218RTET?
The soft-start time for TPS54218RTET is calculated as tSS = CSS × 0.803 V / ICHG, where ICHG = 2.07 μA (typical) and CSS is the capacitor on the SS pin. For example, a 100-nF capacitor yields tSS ≈ 39 ms. The SS pin discharges fully before restart after fault conditions, ensuring repeatable ramp-up behavior in TPS54218RTET-based power systems.
Can TPS54218RTET be synchronized to an external 1-MHz clock?
Yes, TPS54218RTET supports external clock synchronization via the RT/CLK pin across 300 kHz to 2 MHz. When driven with a clean 1-MHz square wave (VIH ≥ 1.6 V, VIL ≤ 0.6 V, tMIN ≥ 75 ns), the internal PLL locks within 14 μs, aligning PH rising edges to CLK falling edges. This eliminates beat frequencies in multi-converter systems and simplifies EMI filtering for TPS54218RTET deployments.
What is the thermal performance of TPS54218RTET on a 2-layer PCB?
On a standard 2-layer PCB (1 oz. copper, no internal planes), TPS54218RTET's junction-to-ambient thermal resistance (θJA) rises to ~75°C/W - limiting continuous 2-A output to ≤55°C ambient. For full-rated operation, TI specifies a 4-layer JEDEC board (2 oz. internal GND planes + 4 thermal vias under PowerPad), achieving θJA = 37°C/W and enabling 2-A output up to 70°C ambient. Derating curves in the TPS54218RTET datasheet SLVS974F confirm this dependency.
TPS54218RTET Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™
- Package/Case:
- 16-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 0.803V
- Voltage - Output (Max):
- 4.5V
- Current - Output:
- 2A
- Frequency - Switching:
- 200kHz ~ 2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WQFN (3x3)
TPS54218RTET FAQ
1.How can I place an order for TPS54218RTET through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54218RTET on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54218RTET reliable?
The price and inventory of TPS54218RTET are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54218RTET is usually 5 days.
3.What payment methods are accepted for TPS54218RTET?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54218RTET transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54218RTET?
TPS54218RTET orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54218RTET order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54218RTET?
For technical support, including TPS54218RTET datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54218RTET requirements.
6.How does Aetrix verify that TPS54218RTET is sourced from the original manufacturer or authorized distributors?
All TPS54218RTET products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54218RTET meets industry standards.
7.What is the process for return or replacement of TPS54218RTET?
All TPS54218RTET units undergo pre-shipment inspection (PSI). If there is an issue with TPS54218RTET, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54218RTET part is unused and in its original packaging.
Return procedure for TPS54218RTET:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS54218RTET Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
