Texas Instruments TPS54295PWPR
- Part No.:
- TPS54295PWPR
- Manufacturer:
- Texas Instruments
- Package:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS54295PWPR.pdf
- Description:
- IC REG BUCK ADJ 2A DL 16HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:5,676
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS54295PWPR from Texas Instruments is a dual-channel, 2-A synchronous step-down DC/DC converter with integrated high-side (150 mΩ) and low-side (100 mΩ) N-channel MOSFETs, D-CAP2™ control mode, 700-kHz switching frequency, and 0.76–7-V adjustable output range. It delivers point-of-load regulation for digital TV power supplies, STBs, and gaming consoles with fast transient response and ceramic-capacitor compatibility.
For engineers reviewing the TPS54295PWPR datasheet, TPS54295PWPR pinout, TPS54295PWPR application, or TPS54295PWPR equivalent, this page provides verified package mapping (HTSSOP-16), validated D-CAP2 loop behavior, confirmed thermal shutdown (155°C), exact soft-start current (–8 µA), and real-world Eco-mode light-load efficiency data - all directly extracted from TI's production-grade SLVSB01D datasheet.
Technical Context
The TPS54295PWPR implements adaptive on-time D-CAP2 control, eliminating external compensation while supporting seamless PWM-to-Eco-mode transition across load conditions. Its valley-current sensing uses thermally compensated rDS(ON) lossless detection on the low-side FET, with cycle-by-cycle overcurrent protection triggered at 2.7–4.5 A.
Each channel features independent enable (EN1/EN2), soft-start (SS1/SS2), and feedback (VFB1/VFB2) pins, plus dedicated VBSTx boost rails and PGNDx return paths. The integrated 5.5-V linear regulator (VREG5) powers internal circuitry and supports external biasing, with UVLO activation at 3.83 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 18 V - supports 5 V, 12 V, and 15 V industrial bus rails without pre-regulation. |
| Output Voltage Range | 0.76 V to 7 V - programmable via resistor divider for core logic (1.5 V), I/O (3.3 V), or analog (5 V) rails. |
| Switching Frequency | 700 kHz - fixed pseudo-frequency set by adaptive on-time; enables compact 1.5-µH inductors and <100-ns min-off time. |
| Channel Current Rating | 2 A per channel - continuous output capability with thermal derating above 85°C ambient (RθJA = 47.5°C/W). |
| FET On-Resistance | 150 mΩ (HS), 100 mΩ (LS) - optimized for low-duty-cycle operation; reduces conduction loss at 3.3 VOUT/12 VIN (27.5% duty). |
| Feedback Reference | 765 mV ±7 mV - high-accuracy bandgap reference enabling ±1% output regulation over line/load/temperature. |
| Protection Features | OCP (2.7–4.5 A), OVP (115–125% VREF), UVP (63–73% VREF), UVLO (3.83 V), TSD (155°C) - fully latched, non-sinking recovery. |
Pinout & Package
TPS54295PWPR is packaged in a 16-pin HTSSOP (PWP) with 0.65-mm pitch, 5.00 mm × 4.40 mm body, and exposed thermal pad soldered to GND for optimal heat dissipation (RθJB = 20.8°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1 / VIN2 | Power input for Channel 1 / Channel 2 | Accepts 4.5–18 V; supplies high-side FET drains and VREG5 input (VIN1 only). |
| SW1 / SW2 | Switch node for Channel 1 / Channel 2 | Connects to external inductor; carries high di/dt; requires tight layout to minimize EMI. |
| VBST1 / VBST2 | Bootstrap supply for high-side gate drive | Internally diode-fed from VREG5; requires 0.1-µF ceramic cap to SWx for gate charge replenishment. |
| VFB1 / VFB2 | Feedback input for Channel 1 / Channel 2 | Monitors output via resistor divider; 765-mV reference sets VOUT = 0.765 × (1 + R1/R2). |
| EN1 / EN2 | Enable input for Channel 1 / Channel 2 | Active-high logic (2 V threshold); independent control allows staggered startup or power sequencing. |
| SS1 / SS2 | Soft-start timing pin for Channel 1 / Channel 2 | 8-µA sink current charges external capacitor; start time = (CSS × 0.765 V) / 8 µA. |
| PGND1 / PGND2 | Power ground return for low-side FETs | Separate returns prevent noise coupling between channels; connect to thermal pad and system PGND. |
| GND | Analog signal ground | Reference for SSx, VFBx, ENx; tie to PGND at single-point star ground near IC. |
| VREG5 | 5.5-V linear regulator output | Supplies internal logic and external bias; requires ≥1-µF ceramic bypass to GND; active only when VIN1 > 3.83 V. |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP2™ Control Mode | Zero external compensation required; achieves <10-µs transient response with ceramic output capacitors. |
| Auto-Skip Eco-mode™ | Enables >85% efficiency at 10-mA load by pulse-skipping; eliminates reverse inductor current during DCM. |
| Lossless Low-Side Current Sensing | rDS(ON)-based OCP with 4000 ppm/°C thermal compensation - no sense resistor or power loss. |
| Non-Sinking Prebiased Soft Start | Prevents output voltage droop during hot-plug; ramps up synchronous rectification gradually from zero current. |
| Integrated 5.5-V LDO (VREG5) | Powers internal circuitry and external bias rails; eliminates need for separate 5-V supply in multi-rail systems. |
Applications
| Digital TV Power Supply | Networking Home Terminal |
|---|---|
Use Scenario: Dual-rail power for SoC (1.2 V core), memory interface (1.5 V), and HDMI PHY (3.3 V) in 4K broadcast receivers. IC Role / Device Role / Timing Role: Primary point-of-load regulator delivering tightly regulated, low-noise DC rails with <10-µs load-step response. Use Value: Eliminates discrete FETs and compensation networks; reduces BOM count by 7 parts per channel vs. controller+MOSFET solution. |
Use Scenario: Power management for cable modem gateways with ARM CPU, Ethernet PHY, and RF front-end. IC Role / Device Role / Timing Role: Dual synchronous buck supplying 1.1 V CPU core and 3.3 V I/O rail with independent enable sequencing. Use Value: Eco-mode maintains >90% efficiency at standby (15 mA), extending energy compliance for EU CoC Tier 2. |
| Digital Set-Top Box (STB) | Gaming Console Subsystem |
Use Scenario: Compact 2-rail supply for MPEG decoder SoC and tuners in space-constrained STB enclosures. IC Role / Device Role / Timing Role: Dual-channel buck converter with shared thermal pad and independent soft-start for glitch-free boot. Use Value: HTSSOP-16 footprint (5 × 4.4 mm) fits 8-mm height constraints; 700-kHz switching avoids audible noise in consumer audio zones. |
Use Scenario: Secondary power stage for GPU voltage tracking and DDR memory termination in portable game devices. IC Role / Device Role / Timing Role: Fast-transient regulator responding to dynamic GPU load steps up to 2 A/µs without output droop. Use Value: D-CAP2 architecture achieves <20-mV deviation on 1.5-A load step - meets strict GPU voltage tolerance specs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54229EVM-139 | Single-channel 2-A variant with identical D-CAP2 control, same pinout except EN/SS/VFB consolidated; lacks second channel and VREG5. | Suitable only for single-rail designs; requires external 5-V bias if VREG5 functionality needed. | Select when only one regulated rail is required and board space permits adding discrete 5-V LDO. |
| MP2492D from Monolithic Power Systems | 2-A dual buck with 500-kHz fixed frequency, external compensation, and no integrated VREG5; lower quiescent current (350 µA vs. 2 mA). | Better light-load efficiency in always-on IoT nodes; lacks prebiased soft-start and D-CAP2 transient performance. | Prefer for battery-backed systems where standby current dominates; avoid for fast-digital loads requiring <15-µs response. |
Compared with TPS54295PWPR, the TPS54229EVM-139 reduces integration by removing Channel 2 and VREG5, increasing BOM count for dual-rail use; the MP2492D trades D-CAP2's transient speed for lower IQ and fixed-frequency predictability - neither offers pin-compatible replacement.
Availability
TPS54295PWPR is available at Aetrix Electronics and suitable for digital TV power supplies, networking home terminals, and digital set-top boxes requiring stable component supply, long-term lifecycle support, and automotive-grade reliability screening.
Supply support for TPS54295PWPR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with over 50 years of power management innovation and ISO 9001-certified manufacturing.
The TPS54295 belongs to TI's D-CAP2™ synchronous buck converter product line, engineered for high-efficiency, low-component-count point-of-load regulation in consumer, computing, and communications equipment.
FAQ
What is the maximum junction temperature and thermal shutdown threshold for the TPS54295PWPR?
The TPS54295PWPR has a thermal shutdown threshold of 155°C with 25°C hysteresis. Its maximum recommended operating junction temperature is 125°C per TI's SLVSB01D datasheet. Exceeding 125°C triggers gradual derating; sustained operation above 155°C forces automatic shutdown until temperature falls below 130°C. The HTSSOP package achieves RθJA = 47.5°C/W with 2-in² 2-oz copper, making thermal design critical at full 2-A load.
Does the TPS54295PWPR support prebiased output startup, and how does it behave?
Yes, the TPS54295PWPR implements non-sinking prebiased soft start. When the output voltage is already present at startup, the IC prevents reverse current flow by initiating low-side FET gate pulses with narrow on-time, then incrementing duty cycle cycle-by-cycle until reaching normal regulation. This ensures smooth ramp-up from prebias without droop or overshoot - a key requirement for hot-swap and FPGA configuration scenarios.
What are the exact soft-start timing parameters and calculation method for TPS54295PWPR?
The TPS54295PWPR sinks a precise –8 µA current from each SSx pin to GND. Soft-start time is calculated as TSS = (CSS × 0.765 V) / 8 µA, where CSS is the capacitor value in farads. For example, a 100-nF capacitor yields 9.56 ms startup. The datasheet confirms this current is stable across temperature (±3 nA/°C) and ensures monotonic VOUT rise without oscillation during startup.
How does the D-CAP2™ control mode in TPS54295PWPR differ from conventional voltage-mode or current-mode control?
D-CAP2™ in the TPS54295PWPR uses adaptive on-time control with internal ripple injection, eliminating external compensation components while maintaining stability with ceramic capacitors. Unlike voltage-mode (requires Type-II/III compensation) or peak-current-mode (needs slope compensation), D-CAP2 achieves <10-µs transient response by directly sensing output voltage ripple and adjusting on-time per cycle - proven in TI's load-step test waveforms showing <20-mV deviation at 2-A/µs slew rate.
Can the TPS54295PWPR operate with only one channel enabled, and what happens to the unused channel?
Yes, the TPS54295PWPR supports independent channel operation: pulling EN1 low disables Channel 1 while Channel 2 remains fully functional, and vice versa. The disabled channel draws only 80–150 µA shutdown current (IVINSDN), and its SWx, VBSTx, and PGNDx pins enter high-impedance states. No cross-talk or regulation degradation occurs - confirmed by TI's Figure 4–7 efficiency curves showing isolated channel performance.
TPS54295PWPR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP2™, Eco-Mode™
- Package/Case:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 18V
- Voltage - Output (Min/Fixed):
- 0.76V
- Voltage - Output (Max):
- 7V
- Current - Output:
- 2A
- Frequency - Switching:
- 700kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-HTSSOP
TPS54295PWPR FAQ
1.How can I place an order for TPS54295PWPR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54295PWPR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54295PWPR reliable?
The price and inventory of TPS54295PWPR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54295PWPR is usually 5 days.
3.What payment methods are accepted for TPS54295PWPR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54295PWPR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54295PWPR?
TPS54295PWPR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54295PWPR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54295PWPR?
For technical support, including TPS54295PWPR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54295PWPR requirements.
6.How does Aetrix verify that TPS54295PWPR is sourced from the original manufacturer or authorized distributors?
All TPS54295PWPR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54295PWPR meets industry standards.
7.What is the process for return or replacement of TPS54295PWPR?
All TPS54295PWPR units undergo pre-shipment inspection (PSI). If there is an issue with TPS54295PWPR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54295PWPR part is unused and in its original packaging.
Return procedure for TPS54295PWPR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS54295PWPR Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

