Texas Instruments TPS54319RTER
- Part No.:
- TPS54319RTER
- Manufacturer:
- Texas Instruments
- Package:
- 16-WFQFN Exposed Pad
- Datasheet:
-
TPS54319RTER.pdf
- Description:
- IC REG BUCK ADJ 3A 16WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS54319RTER from Texas Instruments is a 2.95–6 V input, 3-A synchronous step-down DC/DC converter with integrated 45-mΩ high-side and low-side MOSFETs, fixed-frequency peak-current-mode control, and 0.827 V ±3% internal voltage reference. It delivers regulated 1.8 V output at up to 3 A in compact point-of-load applications such as LCD displays and set-top boxes.
For engineers reviewing the TPS54319RTER datasheet, TPS54319RTER pinout, TPS54319RTER application, or TPS54319RTER equivalent, key selection considerations include its 300–2000 kHz adjustable switching frequency, thermal shutdown (165°C), power-good output with 2% hysteresis, and support for slow-start sequencing via SS/TR pin.
Technical Context
The TPS54319RTER implements constant-frequency peak-current-mode control with internal slope compensation to prevent subharmonic oscillation across duty cycles. Its error amplifier features 245 m℧ transconductance during regulation and reduced gm (79 m℧) during slow start to improve transient response.
Switching is synchronized via PLL on the RT/CLK pin, supporting external clock input or resistor-programmed frequency (e.g., 400–600 kHz with 400 kΩ). The BOOT-PH UVLO (2.2 V) enables near-100% duty-cycle operation, while frequency foldback protects during overcurrent events.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.95 V to 6 V - supports single-cell Li-ion, 3.3 V, and 5 V rails without external LDO pre-regulation. |
| Output Current | 3 A continuous - sustained delivery enabled by thermally enhanced 3×3 mm QFN package and dual 45-mΩ MOSFETs. |
| Reference Voltage | 0.827 V ±3% over 0°C to 85°C - sets minimum output voltage and defines feedback divider ratio accuracy. |
| Switching Frequency | 300–2000 kHz - adjustable via RT resistor or external clock; higher frequencies reduce inductor size but increase switching loss. |
| Power Good Threshold | 93% to 107% of VREF - open-drain PWRGD asserts low outside this window, enabling system-level fault detection and sequencing. |
| Quiescent Current | 360 µA typical at VIN = 5 V - enables high light-load efficiency; drops to <5 µA in shutdown mode. |
| Thermal Shutdown | 165°C with 15°C hysteresis - protects against sustained overload; recovery requires junction cooling below 150°C. |
Pinout & Package
TPS54319RTER uses a thermally enhanced 3 mm × 3 mm, 16-pin QFN package with exposed PowerPAD (Pin 17) for GND connection and thermal dissipation. The package supports ≤51.7°C/W junction-to-ambient thermal resistance on standard PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pins 1, 2, 16) | Input supply rail | Accepts 2.95–6 V; multiple pins reduce trace resistance and improve current handling. |
| PH (Pins 10, 11, 12) | Switch node | Connects to inductor; carries high di/dt switching current; must be routed with minimal loop area. |
| BOOT (Pin 13) | High-side gate drive supply | Requires 0.1 µF X7R/X5R ceramic capacitor to PH; UVLO disables high-side FET if BOOT-PH < 2.2 V. |
| VSENSE (Pin 6) | Error amplifier inverting input | Compares feedback voltage to 0.827 V reference; sets output via R1/R2 divider; max input current 7 nA. |
| COMP (Pin 7) | Error amplifier output | Drives PWM comparator; connects to RC compensation network; gm = 245 m℧ during regulation. |
| EN (Pin 15) | Enable / UVLO control | Pull <1.18 V to disable; internal 1.25 V threshold with hysteresis; floating enables default operation. |
| RT/CLK (Pin 8) | Frequency programming | Resistor-to-GND sets frequency (300–2000 kHz); also accepts external clock with 75 ns min pulse width. |
| SS/TR (Pin 9) | Slow-start / tracking control | 2.2 mA internal charge current sets ramp time; regulates to lower of SS/TR voltage or 0.827 V reference. |
| PWRGD (Pin 14) | Power-good status | Open-drain output; low when VOUT <93% or >107% of target; max 100 Ω on-resistance at 3 mA sink. |
| GND (Pins 3, 4) | Power ground return | Must connect directly to PowerPAD; forms low-inductance path for high-side switch return current. |
| AGND (Pin 5) | Analog ground reference | Separate from power GND; ties to local analog ground plane near VSENSE/COMP to minimize noise coupling. |
| PowerPAD (Pin 17) | Thermal & electrical GND | Exposed pad; requires ≥4 thermal vias to inner/outer ground planes for thermal performance and EMI reduction. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated dual MOSFETs | 45-mΩ high-side and low-side FETs enable >90% efficiency at 3 A, eliminating external switch drivers and layout complexity. |
| Adjustable switching frequency | 300–2000 kHz range allows optimization of inductor size vs. efficiency-e.g., 2 MHz enables 1 µH inductors in space-constrained designs. |
| Programmable slow start | SS/TR pin with 2.2 mA internal current source enables precise control of output ramp time and supports power sequencing with external supplies. |
| UV/OV power-good monitoring | PWRGD provides system-level fault signaling with 2% hysteresis and 93–107% VREF window-critical for FPGA/CPU rail validation. |
| Synchronization capability | RT/CLK pin includes PLL for alignment to external clocks-reduces beat frequencies and EMI in multi-rail systems. |
| Thermal protection | 165°C shutdown with 15°C hysteresis prevents permanent damage during overload; recovery requires thermal cooldown before restart. |
Applications
| Consumer Set-Top Box Power | LCD Display Bias Supply |
|---|---|
|
Use Scenario: Powers SoC core logic and memory interfaces in cable/satellite receivers requiring stable 1.2 V or 1.8 V at up to 3 A. IC Role / Device Role / Timing Role: Primary buck regulator delivering tightly regulated POL voltage; PWRGD signals SoC reset controller upon valid rail. Use Value: Integrated MOSFETs and 2-MHz capability shrink solution size by >30% vs. discrete controllers; 0.827 V reference enables accurate low-VOUT scaling. |
Use Scenario: Generates 3.3 V or 5 V bias for LCD column drivers and timing controllers in portable monitors and signage panels. IC Role / Device Role / Timing Role: Secondary buck stage stepping down 5 V or 12 V intermediate rail; SS/TR enables soft-start to avoid panel flicker during power-up. Use Value: 300 kHz–2 MHz frequency adjustability allows optimal tradeoff between efficiency (low fSW) and capacitor size (high fSW) for display EMI compliance. |
| Home Gateway CPE Equipment | Industrial IoT Sensor Hub |
|
Use Scenario: Supplies 1.8 V and 3.3 V rails to Wi-Fi/BT SoCs and Ethernet PHYs in residential routers and modems. IC Role / Device Role / Timing Role: Dual-output implementation using two TPS54319RTERs with synchronized RT/CLK pins to suppress inter-rail beat noise. Use Value: Synchronization eliminates heterodyne tones in RF-sensitive environments; EN pin programmability supports staggered startup per subsystem. |
Use Scenario: Powers microcontroller, wireless transceiver, and analog front-end in battery-backed edge nodes deployed in factory automation. IC Role / Device Role / Timing Role: High-efficiency POL regulator operating from wide-input 3.6–5.5 V battery or USB supply; quiescent current <5 µA in shutdown extends runtime. Use Value: 360 µA IQ enables >85% efficiency at 10 mA load; thermal shutdown (165°C) ensures reliability in unventilated enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54318RTER | Pin-compatible but rated for 2.95–6 V input and 3 A output with identical QFN-16 package and pinout; lacks PWRGD output. | Cannot provide power-good signaling for system sequencing or fault reporting; unsuitable where rail validation is required. | Select TPS54318RTER only if PWRGD is unused and cost minimization is prioritized over monitoring capability. |
| MP2315DJ-LF-Z | Monolithic 3 A buck with 4.5–26 V input, 0.8 V reference, and 350–2200 kHz fSW; 8-pin SOIC package, no SS/TR or synchronization. | Higher input voltage range suits 12 V/24 V industrial inputs; lacks tracking, sequencing, and clock sync-limits multi-rail coordination. | Choose MP2315DJ-LF-Z for wider VIN applications where compact SOIC footprint is acceptable and advanced control features are unnecessary. |
Compared with TPS54319RTER, TPS54318RTER omits PWRGD for lower cost in non-critical rails, while MP2315DJ-LF-Z trades control flexibility for broader input range and simpler layout-making TPS54319RTER optimal for 3–5 V systems needing sequencing, monitoring, and EMI control.
Availability
TPS54319RTER is available at Aetrix Electronics and suitable for consumer electronics, industrial IoT sensor hubs, and LCD display power systems requiring stable component supply, long-term lifecycle support, and consistent parametric performance.
Supply support for TPS54319RTER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion and automotive-grade reliability.
The TPS54319RTER belongs to TI's SWIFT™ synchronous buck converter family, designed specifically for space-constrained, high-density point-of-load applications demanding precision regulation, thermal robustness, and flexible sequencing.
FAQ
What is the minimum controllable on-time for TPS54319RTER?
The TPS54319RTER has a minimum controllable on-time of 65 ns at full 3 A load and 120 ns at no load. This parameter limits the maximum achievable input-to-output voltage ratio at high switching frequencies-for example, at 2 MHz and 1.8 V output, VIN must remain ≤5.5 V to maintain regulation. Designers must verify on-time margin using the worst-case VIN and VOUT combination in their application.
How does the TPS54319RTER implement power-good monitoring?
The TPS54319RTER uses an internal comparator to monitor VSENSE against 93% and 107% of the 0.827 V reference. When VOUT falls below 93% or rises above 107% of target, the open-drain PWRGD pin pulls low (≤0.6 V at 3 mA sink). Hysteresis is fixed at 2% of VREF, and the output remains asserted until VOUT re-enters the valid window-enabling reliable system reset and sequencing control in the TPS54319RTER design.
Can TPS54319RTER operate with 100% duty cycle?
Yes-the TPS54319RTER supports near-100% duty cycle operation as long as BOOT-PH voltage remains above 2.2 V. When BOOT-PH drops below this threshold, the high-side MOSFET is disabled and the low-side FET conducts continuously, maintaining output regulation during dropout conditions. This behavior is enabled by the internal BOOT UVLO circuit and allows operation with VIN as low as ~VOUT + 0.3 V under light loads.
What is the role of the SS/TR pin in TPS54319RTER?
The SS/TR pin in the TPS54319RTER serves dual functions: slow-start control and voltage tracking. Internally sourced with 2.2 mA, it charges an external capacitor to set output ramp time; the error amplifier regulates to the lower of SS/TR voltage or 0.827 V reference. During tracking, it accepts external voltage references to coordinate startup with other rails-ensuring repeatable, controlled power-up sequences in multi-supply systems using the TPS54319RTER.
How is switching frequency programmed on TPS54319RTER?
Switching frequency on the TPS54319RTER is programmed via a resistor from RT/CLK pin to GND, setting frequency from 300 kHz to 2000 kHz. With a 400 kΩ resistor, typical fSW is 400–600 kHz. The pin also accepts external clock signals (300–2000 kHz, min 75 ns pulse width), and includes a PLL for synchronization-allowing precise timing alignment across multiple TPS54319RTER devices in complex power architectures.
TPS54319RTER Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™
- Package/Case:
- 16-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 0.827V
- Voltage - Output (Max):
- 4.5V
- Current - Output:
- 3A
- Frequency - Switching:
- 300kHz ~ 2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WQFN (3x3)
TPS54319RTER FAQ
1.How can I place an order for TPS54319RTER through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54319RTER on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54319RTER reliable?
The price and inventory of TPS54319RTER are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54319RTER is usually 5 days.
3.What payment methods are accepted for TPS54319RTER?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54319RTER transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54319RTER?
TPS54319RTER orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54319RTER order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54319RTER?
For technical support, including TPS54319RTER datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54319RTER requirements.
6.How does Aetrix verify that TPS54319RTER is sourced from the original manufacturer or authorized distributors?
All TPS54319RTER products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54319RTER meets industry standards.
7.What is the process for return or replacement of TPS54319RTER?
All TPS54319RTER units undergo pre-shipment inspection (PSI). If there is an issue with TPS54319RTER, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54319RTER part is unused and in its original packaging.
Return procedure for TPS54319RTER:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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