Texas Instruments TPS54320RHLR

Overview

TPS54320 from Texas Instruments is a 4.5–17-V input, 3-A synchronous step-down DC/DC converter with integrated 57-mΩ/50-mΩ MOSFETs, 0.8-V ±1% reference, and adjustable 200-kHz to 1.2-MHz switching frequency. It delivers regulated output for FPGA/DSP point-of-load rails, features monotonic start-up into prebiased outputs, hiccup overcurrent protection, and operates across –40°C to 150°C junction temperature.

For engineers reviewing the TPS54320 datasheet, TPS54320 pinout, TPS54320 application, or TPS54320 equivalent, key selection considerations include split power rail support (PVIN = 1.6–17 V), RT/CLK synchronization capability, PWRGD open-drain fault reporting, SS/TR-controlled soft-start/tracking, and thermal pad–dependent thermal performance in the 3.5-mm × 3.5-mm VQFN package.

Technical Context

The TPS54320 implements fixed-frequency peak current mode control with internal slope compensation to prevent subharmonic oscillation across full duty cycle range. Its dual-input architecture separates control supply (VIN: 4.5–17 V) from power stage input (PVIN: 1.6–17 V), enabling flexible biasing in multi-rail systems.

Protection includes cycle-by-cycle high-side current limiting (4.2–6.2 A), bidirectional low-side sourcing/sinking limits (3.8–5.8 A / 1–2.6 A), BOOT-PH UVLO (2.1–3 V), and thermal shutdown at 160–175°C with 10°C hysteresis. The error amplifier has 1300 μA/V transconductance and supports external compensation via COMP pin.

Key Specifications

Pinout & Package

The TPS54320 is housed in a thermally enhanced 14-pin VQFN package (3.5 mm × 3.5 mm) with an exposed thermal pad that must be soldered to PCB ground for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-down converter applications.

Compared with TPS54320, TPS54620RHLR offers direct upgrade path for higher current without layout change, while LM5143ARGER extends input voltage range at cost of added external components and loss of pin compatibility - neither is drop-in replacement outside their specified domains.

Availability

TPS54320 is available at Aetrix Electronics and suitable for communications infrastructure, FPGA power delivery, and medical imaging equipment requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for TPS54320 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, designing and manufacturing analog ICs, embedded processors, and power management solutions for industrial, automotive, and communications markets.

The TPS54320 belongs to TI's SWIFT™ synchronous buck converter product line, engineered specifically for high-efficiency, space-constrained point-of-load applications in networking, test equipment, and FPGA-based systems.

FAQ

What is the minimum output voltage achievable with the TPS54320?

TPS54320 achieves a minimum output voltage of 0.8 V, set by its internal voltage reference with ±1% accuracy across –40°C to 150°C. This value is fixed and cannot be lowered further, as the reference is trimmed and not adjustable. The TPS54320 datasheet confirms this in Section 6.5 under "Voltage Reference" with typical value 0.800 V and min/max bounds of 0.792 V and 0.808 V. Output voltages below 0.8 V require external reference injection or a different regulator.

Can the TPS54320 operate with 100% duty cycle, and what conditions must be met?

Yes, the TPS54320 can operate at 100% duty cycle provided the BOOT-PH voltage remains above the UVLO threshold of 2.1 V (typical). This condition is satisfied when the boot capacitor is adequately sized and the PH node switching activity maintains sufficient recharge. The device's functional description explicitly states it supports 100% duty cycle operation as long as BOOT-PH voltage stays above the preset UVLO level - critical for ultra-low dropout applications like 3.3-V-to-3.0-V conversion.

How does the TPS54320 handle start-up into a prebiased output voltage?

The TPS54320 implements safe monotonic start-up into prebiased outputs by disabling the low-side MOSFET until the SS/TR pin voltage exceeds the VSENSE pin voltage. This prevents reverse current flow from the precharged output into the converter. The feature is confirmed in the device description and Section 7.3.6, which states the low-side FET is not allowed to turn on during monotonic prebiased start-up - a key reliability feature for hot-swap and multi-rail systems.

What is the purpose of the separate VIN and PVIN pins on the TPS54320?

The separate VIN and PVIN pins enable split power rail operation: VIN (4.5–17 V) powers internal control circuitry, while PVIN (1.6–17 V) supplies the power stage. This allows efficient generation of very low output voltages (e.g., 1.0 V) from intermediate buses as low as 1.6 V, improving light-load efficiency and reducing heat generation in the control section. The distinction is documented in Features, Description, and Section 7.3.3.

Does the TPS54320 support external synchronization, and how is it configured?

Yes, the TPS54320 supports external clock synchronization via the RT/CLK pin. When driven with a clean CMOS clock signal, the internal PLL locks to the falling edge of the external clock, aligning switching frequency and phase. Configuration requires disabling the RT resistor and applying clock signal with amplitude between 0.8 V and 2 V logic thresholds. This capability is detailed in Pin Functions, Features, and Section 7.1, enabling EMI reduction in noise-sensitive systems.