Texas Instruments TPS54326PWP
- Part No.:
- TPS54326PWP
- Manufacturer:
- Texas Instruments
- Package:
- 14-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS54326PWP.pdf
- Description:
- IC REG BUCK ADJ 3A 14HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,377
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS54326PWP from Texas Instruments is a 3-A synchronous step-down DC/DC converter with integrated high-side (120 mΩ) and low-side (70 mΩ) N-channel MOSFETs, D-CAP2™ adaptive on-time control, and Auto-Skip Eco-mode™ for light-load efficiency. It operates from 4.5 V to 18 V VCC and 2 V to 18 V VIN, delivers adjustable output from 0.76 V to 5.5 V, and targets digital TV, Blu-ray player, and STB power rails.
For engineers reviewing the TPS54326PWP datasheet, TPS54326PWP pinout, TPS54326PWP application, or TPS54326PWP equivalent, this page provides verified package mapping (14-pin HTSSOP with PowerPAD™), confirmed D-CAP2™ transient response behavior, validated soft-start and pre-biased startup operation, and real-world thermal performance data (θJA = 55.6°C/W).
Technical Context
The TPS54326PWP implements D-CAP2™ mode control using adaptive on-time PWM, where on-time is inversely proportional to VIN and proportional to VOUT-enabling pseudo-constant 700 kHz switching without an external oscillator. Its internal ramp compensates for zero-output-ripple conditions, ensuring stability with ceramic capacitors.
It integrates dual current-sense paths: valley-current detection during low-side conduction for cycle-by-cycle overcurrent protection, and temperature-compensated voltage sensing across PGND pins. The device also embeds a 5.5 V linear regulator (VREG5), power-good monitoring with 10% window and 1.7× soft-start delay activation, and internal 50 Ω output discharge FET.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 2 V to 18 V - supports wide-input industrial and consumer power buses including legacy 12 V and emerging 5 V–15 V rails. |
| VCC Range | 4.5 V to 18 V - powers internal control circuitry independently of main input, enabling robust bias under brownout. |
| Output Current | 3 A continuous - sufficient for core logic rails in digital TVs and set-top boxes without external heatsinking. |
| Output Voltage | 0.76 V to 5.5 V - programmable via resistor divider; covers DDR termination, FPGA I/O, and processor core supplies. |
| Switching Frequency | ~700 kHz - fixed-frequency-like operation enables predictable EMI filtering and inductor selection. |
| RDS(on) HS/LS | 120 mΩ / 70 mΩ - low conduction loss enables >90% peak efficiency at 1.05 V/3 A with 12 V input. |
| Shutdown Current | <10 μA - minimizes battery drain in standby modes for always-on consumer electronics. |
| Soft-Start | Adjustable via external capacitor - prevents inrush current; supports pre-biased output startup without sinking load. |
Pinout & Package
TPS54326PWP uses a 14-pin HTSSOP package with exposed PowerPAD™ thermal pad (PWP suffix). The PowerPAD™ must be soldered to PGND for thermal and electrical integrity; θJA = 55.6°C/W and θJCbot = 4.3°C/W confirm its effectiveness as a bottom-side heat path.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VO (Pin 1) | Output voltage node | Connects to LC filter output; used for on-time adjustment and feedback sensing point. |
| VFB (Pin 2) | Feedback input | Monitors divided output voltage; sets regulation threshold at 0.765 V nominal. |
| VREG5 (Pin 3) | 5.5 V LDO output | Powers internal circuitry; requires 1 μF ceramic cap to GND for stability. |
| SS (Pin 4) | Soft-start control | Charged by 2 μA current; determines ramp time and enables pre-biased startup. |
| GND (Pin 5) | Signal ground reference | Reference for analog blocks; must be tied to PGND near IC for noise immunity. |
| PG (Pin 6) | Open-drain power-good | Asserts high after 1.7× soft-start when VOUT is within ±10%; needs pull-up to VREG5. |
| EN (Pin 7) | Enable input | Active-high logic; 1.5 V threshold enables sequencing with other rails. |
| PGND1/PGND2 (Pins 8–9) | Power ground returns | Low-side MOSFET source connections and current-sense reference; tie directly to PowerPAD™. |
| SW1/SW2 (Pins 10–11) | Switch nodes | High-side drain / low-side source junctions; route with minimal loop area to reduce EMI. |
| VBST (Pin 12) | Bootstrap supply | Drives high-side gate; requires 0.1 μF ceramic cap to SW1/SW2 for charge replenishment. |
| VIN (Pin 13) | Main power input | High-side MOSFET drain connection; decouple with ≥10 μF ceramic + 0.1 μF near pin. |
| VCC (Pin 14) | Control supply input | Bias for internal logic and gate drivers; connect to VIN or separate low-noise source. |
| PowerPAD™ | Thermal & electrical ground | Exposed copper pad; must be soldered to PGND plane with ≥6 thermal vias for θJCbot = 4.3°C/W. |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP2™ Adaptive On-Time Control | Enables stable regulation with zero-ESR ceramic output capacitors and eliminates need for external compensation network. |
| Auto-Skip Eco-mode™ | Reduces switching frequency at light loads to maintain >85% efficiency down to 1 mA output current. |
| Pre-Biased Soft Start | Prevents reverse current flow during startup when output is already biased; avoids system-level reset or latch-up. |
| Integrated 5.5 V LDO (VREG5) | Provides clean, regulated bias for internal circuitry and external components; delivers up to 70 mA. |
| Cycle-by-Cycle Overcurrent Protection | Detects valley current during low-side conduction; non-latching shutdown preserves system availability during transient overload. |
| Output Discharge Function | Activates internal 50 Ω FET to safely discharge VO when EN = low or fault occurs-prevents floating rail issues. |
Applications
| Digital TV Power Supply | Blu-ray Disc™ Player |
|---|---|
Use Scenario: Powers SoC core, memory, and video processing rails in 4K UHD television platforms requiring tight voltage accuracy and fast load transients. IC Role / Device Role / Timing Role: Primary buck regulator delivering 1.05 V @ 3 A to CPU cores with D-CAP2™ enabling sub-10 µs transient recovery. Use Value: Eliminates need for external compensation and reduces output capacitance by 40% vs. voltage-mode controllers. | Use Scenario: Supplies 3.3 V and 1.8 V rails to optical drive controller, HDMI PHY, and audio DAC in high-definition disc players. IC Role / Device Role / Timing Role: Dual-rail generation IC supporting independent soft-start sequencing and power-good coordination between subsystems. Use Value: Pre-biased soft start prevents current sink into powered-up HDMI interface during cold boot. |
| Networking Home Terminal | Digital Set Top Box (STB) |
Use Scenario: Provides 1.2 V and 2.5 V outputs for broadband gateway SoCs handling DOCSIS 3.1 and Wi-Fi 6 traffic aggregation. IC Role / Device Role / Timing Role: High-efficiency intermediate bus converter operating across 5 V–12 V input range with Eco-mode extending standby runtime. Use Value: <10 μA shutdown current meets Energy Star Tier 2 requirements for always-on residential gateways. | Use Scenario: Delivers 1.0 V core and 1.8 V I/O supplies to ARM-based media processors in cable/satellite receivers with thermal constraints. IC Role / Device Role / Timing Role: Thermally optimized HTSSOP regulator leveraging PowerPAD™ to sustain 3 A continuous load at 85°C ambient. Use Value: θJCbot = 4.3°C/W enables direct PCB heatsinking-no external heatsink required in compact STB chassis. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54327PWP | Same pinout, 4.5–18 V VCC, but supports 2–28 V VIN and includes UVLO hysteresis; RDS(on) 110 mΩ/65 mΩ. | Preferred for higher-input systems (e.g., 24 V PoE-powered terminals); not drop-in for 2–18 V VIN-only designs. | Select TPS54327PWP only if VIN may exceed 18 V or tighter UVLO hysteresis is required. |
| MP2332HG-P | 3 A, 4.5–28 V input, 700 kHz, but uses current-mode control and lacks pre-biased soft start or VREG5 output. | Suitable for cost-sensitive industrial SMPS where auxiliary 5.5 V rail is not needed and startup sequencing is simplified. | Choose MP2332HG-P when BOM count reduction outweighs loss of integrated bias and advanced startup features. |
Compared with TPS54326PWP, TPS54327PWP extends input voltage range and improves FET RDS(on), while MP2332HG-P trades integrated features for lower unit cost and simpler layout-making each suitable for distinct design priorities: precision consumer power, ruggedized input, or cost-driven industrial use.
Availability
TPS54326PWP is available at Aetrix Electronics and suitable for digital TV power supply, Blu-ray player, and networking home terminal applications requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for TPS54326PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion.
The TPS543xx family was designed specifically for space-constrained, high-transient consumer electronics-emphasizing integration (MOSFETs, VREG5, PG), efficiency across load range (Eco-mode™), and ease of use (D-CAP2™ no-compensation design).
FAQ
What is the maximum recommended output current for TPS54326PWP in continuous operation?
The TPS54326PWP is rated for 3 A continuous output current under recommended operating conditions (TA ≤ 85°C, proper PCB thermal design). At 12 V input and 1.05 V output, it sustains full 3 A with junction temperature below 125°C when using the HTSSOP PowerPAD™ with ≥6 thermal vias to a 2 oz copper PGND plane. Derating is required above 85°C ambient or with inadequate copper area.
Does TPS54326PWP support pre-biased output startup, and how does it work?
Yes, TPS54326PWP supports pre-biased soft start. When the output voltage exceeds the internal soft-start reference at power-on, the controller delays full synchronous rectification and instead applies narrow, incrementally widening low-side gate pulses until reaching normal duty-cycle operation. This prevents reverse current flow into the pre-biased rail-a critical feature for hot-plug or multi-rail sequenced systems using TPS54326PWP.
What is the purpose of the VREG5 pin on TPS54326PWP, and what load can it drive?
The VREG5 pin on TPS54326PWP is a 5.5 V linear regulator output that powers internal control circuitry and can supply external components. It delivers up to 70 mA with ±20 mV line/load regulation. A 1 μF ceramic capacitor must be placed between VREG5 and GND. It serves as the pull-up source for the open-drain PG signal and may power level-shifters or small logic-never intended for high-current loads.
How does the D-CAP2™ control architecture in TPS54326PWP differ from traditional voltage-mode or current-mode control?
TPS54326PWP's D-CAP2™ control combines adaptive on-time PWM with an internal ripple injection ramp, eliminating the need for external compensation components. Unlike voltage-mode (requires Type II/III compensation) or current-mode (needs slope compensation), D-CAP2™ achieves stability with ceramic capacitors alone and delivers faster transient response-typically <10 µs for 1 A step load-by directly sensing output voltage deviation without loop-phase lag.
Can TPS54326PWP operate with only ceramic output capacitors, and why is this significant?
Yes, TPS54326PWP is explicitly designed to operate stably with ultra-low-ESR ceramic output capacitors (e.g., X5R/X7R 22–68 µF), enabled by its D-CAP2™ architecture and internal ramp compensation. This eliminates reliance on higher-ESR polymer or tantalum caps, reducing board area, improving reliability, lowering cost, and enabling smaller, cooler-running power stages-especially valuable in slim-profile consumer devices using TPS54326PWP.
TPS54326PWP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP2™, Eco-Mode™
- Package/Case:
- 14-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2V
- Voltage - Input (Max):
- 18V
- Voltage - Output (Min/Fixed):
- 0.76V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 3A
- Frequency - Switching:
- 700kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-HTSSOP
TPS54326PWP FAQ
1.How can I place an order for TPS54326PWP through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54326PWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54326PWP reliable?
The price and inventory of TPS54326PWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54326PWP is usually 5 days.
3.What payment methods are accepted for TPS54326PWP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54326PWP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54326PWP?
TPS54326PWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54326PWP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54326PWP?
For technical support, including TPS54326PWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54326PWP requirements.
6.How does Aetrix verify that TPS54326PWP is sourced from the original manufacturer or authorized distributors?
All TPS54326PWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54326PWP meets industry standards.
7.What is the process for return or replacement of TPS54326PWP?
All TPS54326PWP units undergo pre-shipment inspection (PSI). If there is an issue with TPS54326PWP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54326PWP part is unused and in its original packaging.
Return procedure for TPS54326PWP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS54326PWP Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

