Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - DC DC Switching Regulators

Texas Instruments TPS54352PWP

Name: TPS54352PWP
Brand: Texas Instruments
SKU: TPS54352PWP
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: TPS54352PWP

Manufacturer:: Texas Instruments

Category:: Voltage Regulators - DC DC Switching Regulators

Package:: 16-PowerTSSOP (0.173", 4.40mm Width)

Datasheet:: TPS54352PWP.pdf

Description:: IC REG BUCK 1.2V 3A 16HTSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:3,034

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

TPS54352PWP from Texas Instruments is a 1.2-V fixed-output, 3-A continuous synchronous buck PWM converter with integrated 100-mΩ high-side MOSFET and external low-side MOSFET/diode support. It operates from 4.5 V to 20 V input, delivers ±1% output voltage accuracy over load/temperature, features internal compensation, 250 kHz or 500 kHz fixed switching frequency, and 180° out-of-phase synchronization capability - used in point-of-load regulation for FPGAs and microprocessors.

For engineers reviewing the TPS54352PWP datasheet, TPS54352PWP pinout, TPS54352PWP application, or TPS54352PWP equivalent, key selection criteria include its 1.2-V fixed output, thermal shutdown at 165°C, UVLO start threshold of 4.49 V, 16-pin TSSOP PowerPAD package, and compatibility with external low-side MOSFETs for efficiency optimization in industrial and embedded power systems.

Technical Context

The TPS54352PWP implements feed-forward PWM modulation with 8 V/V modulator gain, adaptive dead-time control to prevent shoot-through, and a true voltage error amplifier (60 dB open-loop gain, 2 MHz unity-gain bandwidth). Its internal slow-start ramps reference voltage over 1150 switching cycles, with programmable timing via RT pin configuration.

It supports bidirectional SYNC operation: outputs falling-edge signal 180° out-of-phase with PH when RT is grounded/floating; accepts external falling-edge sync input when RT is resistor-programmed. The device integrates undervoltage lockout (UVLO), hiccup-mode overcurrent protection (4.5 ms hiccup time at 500 kHz), and thermal shutdown with 7°C hysteresis.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Voltage	Fixed 1.2 V, ±1% accuracy over 100 mA–3 A load and −40°C to 125°C junction temperature.
Input Voltage Range	4.5 V to 20 V - supports wide industrial input rails including 5 V, 12 V, and 19 V systems.
Continuous Output Current	3 A - sustained delivery without derating under typical PCB layout with PowerPAD soldered.
Switching Frequency	250 kHz (RT grounded) or 500 kHz (RT floating) - fixed options eliminate external timing components.
High-Side rDS(ON)	100 mΩ (typ.) at VIN = 12 V - enables high efficiency (>90% at 3 A, 12 V→1.2 V) and low thermal dissipation.
UVLO Start Threshold	4.49 V (typ.) - prevents startup until input stabilizes above minimum operating voltage.
Thermal Shutdown	165°C trip point with 7°C hysteresis - protects against sustained overload or poor heatsinking.
Power Good Accuracy	97% output threshold with 2–4 ms rising-edge delay - provides reliable system sequencing feedback.

Pinout & Package

TPS54352PWP uses a thermally enhanced 16-pin HTSSOP (PWP) PowerPAD package with exposed thermal pad connected to PGND/AGND. The PowerPAD must be soldered to PCB copper for thermal performance and electrical integrity.

Pin/Terminal	Circuit Role	Design Meaning
1, 2 VIN	Input supply rail	4.5–20 V primary input; requires local 10-µF ceramic bypass capacitor placed adjacent to pins.
3 UVLO	Undervoltage lockout adjust	External resistor divider overrides default 4.49 V start threshold; internal 320 kΩ/125 kΩ divider.
4 PWRGD	Open-drain power-good indicator	Asserts low during fault conditions (UVLO, overcurrent, thermal shutdown, slow-start, VSENSE out-of-range).
5 RT	Frequency setting	Ground = 250 kHz; float = 500 kHz; resistor-to-AGND sets 250–700 kHz - also controls SYNC I/O mode.
6 SYNC	Bidirectional sync interface	Outputs 180° out-of-phase falling edge when RT grounded/floating; accepts falling-edge sync input when RT resistor-programmed.
7 ENA	Enable/disable control	Pulled high internally; <0.5 V disables switching and resets slow-start; no external pullup required.
8 COMP	Error amplifier output	Internal node - no external connection permitted; drives PWM comparator and compensation network.
9 VSENSE	Feedback input	Inverting input of error amplifier; compares output voltage (via resistor divider) to 0.891 V internal reference.
10 AGND	Analog ground reference	Low-noise analog return; must be tied to PGND and PowerPAD to minimize noise coupling into control loop.
11 PGND	Power ground return	High-current return path for LSG driver and internal MOSFET; connects to PowerPAD for thermal conduction.
12 VBIAS	Internal bias supply	8.0 V regulated output (7.5–8.0 V); powers internal analog circuits and LSG driver; requires 1.0-µF X7R/X5R ceramic cap.
13 LSG	Low-side gate driver output	100-mA capable driver for external n-channel MOSFET; enables synchronous rectification for >90% efficiency.
14, 15 PH	Phase node connection	Switching node connecting to LC filter inductor; carries high di/dt current - layout critical for EMI control.
16 BOOT	Bootstrap capacitor connection	Connects 0.1-µF ceramic cap to PH; supplies gate drive voltage for high-side MOSFET during each switching cycle.

Key Features

Feature	Design Value
Integrated 100-mΩ high-side MOSFET	Reduces BOM count and PCB area vs. controller-only solutions; eliminates external high-side driver design complexity.
180° out-of-phase synchronization	Enables dual-phase operation with shared input capacitor, cutting RMS input ripple current by ~30% and reducing required input capacitance.
Internally compensated control loop	Eliminates need for external compensation components - simplifies design, improves stability margin across line/load/temperature.
Adaptive dead-time control	Prevents shoot-through by dynamically delaying high-side turn-on until low-side gate voltage drops below 1 V, and vice versa.
Hiccup-mode overcurrent protection	Disables switching for 4.5 ms (at 500 kHz), then retries - avoids thermal runaway while enabling automatic recovery after transient faults.
Thermally enhanced PowerPAD package	42.1°C/W junction-to-ambient (with soldered pad) - enables 3-A operation at 70°C ambient without forced airflow or heatsink.

Applications

Point-of-Load Regulation for FPGA Core	Industrial CPU Power Supply
Use Scenario: Powers 1.2-V core rail of Xilinx Spartan-6 or Intel Cyclone IV FPGA during configuration and active logic operation. IC Role / Device Role / Timing Role: Synchronous buck regulator delivering up to 3 A with fast transient response to handle dynamic current steps during logic switching. Use Value: Internal 100-mΩ MOSFET and feed-forward modulation enable <100-ns load-step response and <1% output deviation - meeting FPGA core voltage tolerance specs.	Use Scenario: Supplies 1.2-V I/O or core voltage to ARM Cortex-A9-based industrial controller operating in −40°C to 85°C ambient. IC Role / Device Role / Timing Role: Primary DC-DC converter with thermal shutdown and UVLO ensuring safe startup and fault containment in unattended equipment. Use Value: 165°C thermal trip with 7°C hysteresis and 4.49 V UVLO start guarantee reliable operation across wide input and temperature ranges.
Embedded DSP Power Management	Medical Imaging Subsystem Rail
Use Scenario: Generates clean 1.2-V supply for TI C674x DSP in portable ultrasound front-end module. IC Role / Device Role / Timing Role: Fixed-output buck converter synchronized to system clock via SYNC pin to reduce EMI in sensitive analog signal chains. Use Value: 180° out-of-phase sync capability allows interleaving with other TPS5435x devices, lowering input capacitor RMS current and easing EMI filtering.	Use Scenario: Provides isolated 1.2-V bias for CCD/CMOS sensor interface ASIC in diagnostic imaging equipment. IC Role / Device Role / Timing Role: Point-of-load regulator with PWRGD output feeding FPGA-based sequencer to ensure power-rail sequencing compliance per IEC 62304. Use Value: 97% power-good threshold with 2-ms delay at 500 kHz ensures accurate detection of valid output before downstream logic initialization.

Point-of-Load Regulation for FPGA Core

Industrial CPU Power Supply

Use Scenario: Powers 1.2-V core rail of Xilinx Spartan-6 or Intel Cyclone IV FPGA during configuration and active logic operation.

IC Role / Device Role / Timing Role: Synchronous buck regulator delivering up to 3 A with fast transient response to handle dynamic current steps during logic switching.

Use Value: Internal 100-mΩ MOSFET and feed-forward modulation enable <100-ns load-step response and <1% output deviation - meeting FPGA core voltage tolerance specs.

Use Scenario: Supplies 1.2-V I/O or core voltage to ARM Cortex-A9-based industrial controller operating in −40°C to 85°C ambient.

IC Role / Device Role / Timing Role: Primary DC-DC converter with thermal shutdown and UVLO ensuring safe startup and fault containment in unattended equipment.

Use Value: 165°C thermal trip with 7°C hysteresis and 4.49 V UVLO start guarantee reliable operation across wide input and temperature ranges.

Embedded DSP Power Management

Medical Imaging Subsystem Rail

Use Scenario: Generates clean 1.2-V supply for TI C674x DSP in portable ultrasound front-end module.

IC Role / Device Role / Timing Role: Fixed-output buck converter synchronized to system clock via SYNC pin to reduce EMI in sensitive analog signal chains.

Use Value: 180° out-of-phase sync capability allows interleaving with other TPS5435x devices, lowering input capacitor RMS current and easing EMI filtering.

Use Scenario: Provides isolated 1.2-V bias for CCD/CMOS sensor interface ASIC in diagnostic imaging equipment.

IC Role / Device Role / Timing Role: Point-of-load regulator with PWRGD output feeding FPGA-based sequencer to ensure power-rail sequencing compliance per IEC 62304.

Use Value: 97% power-good threshold with 2-ms delay at 500 kHz ensures accurate detection of valid output before downstream logic initialization.

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck regulator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS54356PWP	Fixed 3.3-V output; identical pinout, package, and feature set except output voltage and UVLO thresholds.	Used where 3.3-V rail is required instead of 1.2 V - no change to layout or external components beyond feedback resistors.	Select TPS54356PWP only if 3.3-V output is needed; not a drop-in replacement for 1.2-V requirement.
LM2678SD-1.2/NOPB	1.2-V fixed-output buck regulator with 5-A rating, but uses external MOSFETs; no SYNC, no PowerPAD, larger SO-8 package.	Suitable for higher-current designs requiring >3 A or discrete MOSFET flexibility; lacks synchronization and thermal performance of PowerPAD.	Choose LM2678SD-1.2/NOPB only when 5-A output or discrete FET control is mandatory; expect higher board area and thermal management effort.

Compared with TPS54356PWP, the TPS54352PWP offers matched thermal and synchronization capability but targets 1.2-V core rails rather than 3.3-V I/O rails; versus LM2678SD-1.2/NOPB, it delivers superior thermal efficiency and smaller footprint via integrated high-side FET and PowerPAD, at the cost of lower max current.

Availability

TPS54352PWP is available at Aetrix Electronics and suitable for industrial automation controllers, medical imaging subsystems, and FPGA-based test equipment requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for TPS54352PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management IC design and manufacturing.

The TPS5435x product line was engineered for high-efficiency, space-constrained point-of-load applications in FPGAs, DSPs, and microprocessors - emphasizing thermal performance, internal integration, and robust protection features.

FAQ

What is the output voltage tolerance of the TPS54352PWP over full load and temperature?

The TPS54352PWP delivers 1.2 V with ±1% output voltage tolerance across 100 mA to 3 A load current and −40°C to +125°C junction temperature, verified per Electrical Characteristics table on page 4 of SLVS519A. This tight regulation is achieved using an internal 0.891 V reference trimmed during production and a high-gain error amplifier. The TPS54352PWP maintains this accuracy without external trimming components.

Can the TPS54352PWP operate without an external low-side MOSFET?

Yes, the TPS54352PWP can operate with only an external Schottky diode connected from PH to PGND, as stated in the Features and Simplified Schematic sections. In this configuration, the integrated pulldown MOSFET supports light-load continuous conduction mode. However, using an external low-side MOSFET driven by the LSG pin improves efficiency - especially above 1 A - and is recommended for optimal thermal performance in the TPS54352PWP design.

How does the SYNC pin function on the TPS54352PWP when RT is grounded?

When the RT pin is grounded, the TPS54352PWP operates at 250 kHz and configures the SYNC pin as an output that generates a falling-edge signal approximately 180° out of phase with the rising edge of the PH pin. This enables seamless interleaving with a second TPS54352PWP or compatible device to reduce input ripple current. A 10-kΩ resistor to ground is mandatory on SYNC in all configurations, per Pin Assignments section.

What thermal performance can be expected from the TPS54352PWP in a standard 2-layer PCB layout?

With the PowerPAD soldered to a 2 oz. copper thermal pad (3″ × 3″, top/bottom planes, thermal vias), the TPS54352PWP achieves 42.1°C/W junction-to-ambient thermal impedance. At 3 A output and 12 V input, typical power dissipation is ~0.9 W, resulting in ~38°C junction rise above 25°C ambient - well within the 125°C max operating junction temperature. Performance degrades significantly without proper PowerPAD soldering.

Does the TPS54352PWP support adjustable output voltage via external resistors?

No, the TPS54352PWP is a fixed 1.2-V output device. Its feedback is internally connected to generate precisely 1.2 V; there is no VSENSE pin accessible for external resistor-divider adjustment. For adjustable-output alternatives in the same family, TI offers the TPS54350 (adjustable version), but it is not pin-compatible with the TPS54352PWP and requires different compensation design.

TPS54352PWP Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: SWIFT™

Package/Case:: 16-PowerTSSOP (0.173", 4.40mm Width)

Packaging:: Bulk

Product Status:: Obsolete

Function:: Step-Down

Output Configuration:: Positive

Topology:: Buck

Output Type:: Fixed

Number of Outputs:: 1

Voltage - Input (Min):: 4.5V

Voltage - Input (Max):: 20V

Voltage - Output (Min/Fixed):: 1.2V

Voltage - Output (Max):: -

Current - Output:: 3A

Frequency - Switching:: 250kHz, 500kHz

Synchronous Rectifier:: Yes

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-HTSSOP

TPS54352PWP FAQ

1.How can I place an order for TPS54352PWP through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS54352PWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS54352PWP reliable?

The price and inventory of TPS54352PWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54352PWP is usually 5 days.

3.What payment methods are accepted for TPS54352PWP?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54352PWP transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TPS54352PWP?

TPS54352PWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS54352PWP order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS54352PWP?

For technical support, including TPS54352PWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54352PWP requirements.

6.How does Aetrix verify that TPS54352PWP is sourced from the original manufacturer or authorized distributors?

All TPS54352PWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54352PWP meets industry standards.

7.What is the process for return or replacement of TPS54352PWP?

All TPS54352PWP units undergo pre-shipment inspection (PSI). If there is an issue with TPS54352PWP, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS54352PWP part is unused and in its original packaging.

Return procedure for TPS54352PWP:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…