Texas Instruments TPS54354PWP
- Part No.:
- TPS54354PWP
- Manufacturer:
- Texas Instruments
- Package:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS54354PWP.pdf
- Description:
- IC REG BUCK 1.8V 3A 16HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,963
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Product details
Overview
TPS54354PWP from Texas Instruments is a 1.8-V fixed-output, synchronous buck PWM converter with integrated 100-mΩ high-side MOSFET and external low-side MOSFET driver (LSG), delivering up to 3-A continuous output current at 95% peak efficiency (12-VIN, 3.3-VOUT, 500-kHz). It features internal compensation, 180° out-of-phase synchronization capability, and operates in a thermally enhanced 16-pin TSSOP PowerPAD package for point-of-load regulation in FPGAs and DSPs.
For engineers reviewing the TPS54354PWP datasheet, TPS54354PWP pinout, TPS54354PWP application, or TPS54354PWP equivalent, key selection considerations include its fixed 1.8-V output, 250–700-kHz adjustable switching frequency via RT pin, internal slow-start time of 2.30 ms (at 500 kHz), UVLO threshold programmability, and open-drain PWRGD status signal with 97% output voltage threshold.
Technical Context
The TPS54354PWP implements feed-forward PWM modulation with an 8 V/V modulator gain, adaptive dead-time control to prevent shoot-through, and a high-performance error amplifier (60 dB open-loop gain, 2-MHz unity-gain bandwidth) referenced to a trimmed 0.891-V internal bandgap. Its bidirectional SYNC pin supports both master (output) and slave (input) modes depending on RT configuration.
It integrates undervoltage lockout with 1.24-V start/1.02-V stop thresholds on the UVLO pin, thermal shutdown at 165°C with 7°C hysteresis, and cycle-by-cycle overcurrent protection triggering hiccup mode after 100-ns current limit violation. The LSG driver delivers 100 mA sink/source with 15-ns rise time and 60-ns deadtime.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.8 V ±1.2% (100 mA–3 A load, TJ = 25°C); enables precise core supply for 1.8-V logic rails. |
| Switching Frequency | 250 kHz (RT grounded), 500 kHz (RT floating), or 250–700 kHz (RT resistor to AGND); sets ripple, filter size, and EMI profile. |
| Continuous Output Current | 3 A; supported by 100-mΩ high-side MOSFET and external low-side FET/diode path. |
| Input Voltage Range | 4.5 V to 20 V; compatible with 5-V, 12-V, and 19-V intermediate bus systems. |
| Thermal Shutdown Threshold | 165°C with 7°C hysteresis; protects against sustained overload or poor PCB thermal design. |
| Power Good Threshold | 97% of nominal output (1.746 V); provides reliable system power sequencing and fault indication. |
| Internal Slow-Start Time | 2.30 ms (10%–90%, fs = 500 kHz); limits inrush current during startup into large output capacitance. |
Pinout & Package
TPS54354PWP uses a 16-pin HTSSOP (PWP) PowerPAD package with exposed thermal pad soldered to PGND/AGND for enhanced thermal performance (θJA = 42.1°C/W with soldered pad).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 VIN | Input supply rail | 4.5–20 V input; requires local 10-µF ceramic bypass close to pins 1/2. |
| 3 UVLO | Undervoltage lockout adjust | External resistor divider overrides default 1.24-V start threshold; prevents premature startup. |
| 4 PWRGD | Open-drain power-good indicator | Drives low when VOUT < 97% or fault occurs; used for system enable sequencing. |
| 5 RT | Frequency setting | Resistor to AGND sets 250–700-kHz switching; floating = 500 kHz, grounded = 250 kHz. |
| 6 SYNC | Bidirectional sync I/O | Outputs falling edge 180° out-of-phase with PH when RT floating; accepts falling-edge sync input when RT resistor used. |
| 7 ENA | Enable control | Logic-high enables operation; <0.5 V disables and resets slow-start; internal 5-µA pullup. |
| 8 COMP | Error amplifier output | Do NOT connect external components; internal node for loop compensation. |
| 9 VSENSE | Feedback input | Monitors output via resistive divider; referenced to 0.891-V internal bandgap. |
| 10 AGND | Analog ground reference | Connect to PGND and PowerPAD; separates noise-sensitive analog circuitry. |
| 11 PGND | Power ground return | Carries high di/dt currents from LSG driver; must tie to AGND and PowerPAD. |
| 12 VBIAS | Internal 8-V bias supply | Provides gate drive for LSG; requires 1.0-µF X7R/X5R ceramic bypass capacitor. |
| 13 LSG | Low-side gate driver output | 100-mA capable driver for external n-channel MOSFET; no series gate resistor recommended. |
| 14, 15 PH | Phase node connection | Connects to LC output filter; carries high-frequency switching current; ties to BOOT capacitor. |
| 16 BOOT | Bootstrap capacitor node | Requires 0.1-µF ceramic cap between BOOT and PH; supplies gate drive for high-side MOSFET. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated high-side MOSFET | 100-mΩ RDS(on) at 12 VIN; reduces conduction loss and eliminates external high-side switch. |
| 180° out-of-phase synchronization | SYNC pin enables dual-converter interleaving to halve input RMS ripple and reduce required input capacitance. |
| Internally compensated control loop | No external compensation components needed; simplifies layout and reduces BOM count for standard applications. |
| Programmable undervoltage lockout | UVLO pin accepts external resistor divider to set custom start/stop thresholds beyond factory defaults. |
| Adaptive dead-time control | Prevents shoot-through by dynamically delaying LSG turn-on until PH voltage drops below 1 V. |
Applications
| Industrial Point-of-Load Regulation | FPGA Core Supply |
|---|---|
|
Use Scenario: Regulating 1.8-V supply for FPGA I/O banks in industrial PLCs with wide input voltage range (12–24 VDC). IC Role / Device Role / Timing Role: Synchronous buck controller providing tightly regulated, low-noise 1.8-V rail with fast transient response to logic switching. Use Value: Internal 100-mΩ MOSFET and 3-A capability eliminate external high-side switch; PWRGD enables safe FPGA configuration sequencing. |
Use Scenario: Delivering stable 1.8-V core voltage to Xilinx Spartan-6 or Intel Cyclone IV FPGA under dynamic load conditions. IC Role / Device Role / Timing Role: Primary DC/DC converter with internal slow-start and 97% PWRGD threshold ensuring clean power-up before configuration. Use Value: 2.30-ms internal slow-start prevents inrush-induced current-limit hiccup; 180° SYNC supports dual-rail designs for higher current or lower ripple. |
| LCD Monitor Logic Supply | DSP Digital Signal Processor Rail |
|
Use Scenario: Generating 1.8-V logic supply for timing controllers and interface ICs in 24-inch LCD monitors powered from 12-V adapter. IC Role / Device Role / Timing Role: Fixed-output buck regulator with thermal shutdown and UVLO protecting against adapter brownouts and overheating. Use Value: 16-pin PowerPAD package enables compact layout; 500-kHz operation allows small 2.2-µH inductor and 22-µF output capacitors. |
Use Scenario: Supplying 1.8-V core voltage to TI C674x or Analog Devices SHARC DSPs in audio processing equipment. IC Role / Device Role / Timing Role: High-efficiency synchronous buck converter with feed-forward modulation for rapid load-step response. Use Value: 8 V/V feed-forward gain maintains constant loop gain across input voltage changes; LSG driver supports optimized external MOSFET selection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54356PWP | Fixed 3.3-V output; identical pinout, package, and feature set except output voltage and internal feedback divider. | Used where 3.3-V logic rail is required instead of 1.8-V; not interchangeable without redesigning feedback network. | Select TPS54356PWP only when 3.3-V output is needed; same layout and thermal design apply. |
| TPS543320RHLR | 4-V to 18-V input, 1.8-V output, 3-A, but uses QFN-18 package with different pinout and integrated MOSFETs (no external LSG). | Higher integration (dual MOSFETs), smaller footprint, but lacks LSG flexibility and SYNC phase control. | Choose TPS543320RHLR for space-constrained designs needing full integration; avoid if external low-side FET optimization is required. |
Compared with TPS54354PWP, TPS54356PWP offers identical functionality at 3.3 V and shares PCB layout compatibility, while TPS543320RHLR trades LSG configurability and 180° SYNC for higher integration and smaller QFN packaging-making it suitable for compact, fixed-feature applications but less flexible for thermal or efficiency tuning.
Availability
TPS54354PWP is available at Aetrix Electronics and suitable for industrial PLCs, FPGA power delivery, LCD monitor logic supplies, and DSP core regulation requiring stable component supply across extended temperature ranges (−40°C to +85°C).
Supply support for TPS54354PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power conversion ICs.
The TPS5435x family was designed specifically for medium-current, high-efficiency point-of-load applications in computing, industrial, and consumer electronics-emphasizing thermal robustness, synchronization flexibility, and minimal external component count.
FAQ
What is the output voltage tolerance of the TPS54354PWP under full load?
The TPS54354PWP delivers a fixed 1.8-V output with ±1.2% tolerance (1.764 V to 1.836 V) across 100 mA to 3-A load current at TJ = 25°C, as specified in the Electrical Characteristics table. This tight regulation ensures compatibility with 1.8-V logic interfaces in FPGAs and DSPs without requiring external trimming.
Can the TPS54354PWP operate without an external low-side MOSFET?
Yes, the TPS54354PWP can operate using only an external Schottky diode connected from PH to PGND, bypassing the LSG pin. The device includes an integrated pulldown MOSFET for light-load CCM operation, though efficiency improves significantly with an external low-side MOSFET driven by the LSG pin.
How does the SYNC pin function in TPS54354PWP when RT is left floating?
When the RT pin is floating, the TPS54354PWP operates at 500 kHz and configures the SYNC pin as an output that generates a falling-edge signal approximately 180° out of phase with the rising edge of the PH pin-enabling seamless interleaved operation with a second TPS5435x device sharing the same input capacitor.
What thermal derating applies to the TPS54354PWP at 85°C ambient?
At TA = 85°C, the TPS54354PWP's maximum allowable power dissipation in the 16-pin PWP package with soldered thermal pad is 0.95 W (per Package Dissipation Ratings table), corresponding to ~1.1-A output current at 12-V input assuming 90% efficiency-requiring careful thermal design for full 3-A operation at elevated ambient.
Is the TPS54354PWP RoHS-compliant and lead-free?
Yes, the TPS54354PWP is manufactured in a RoHS-compliant, lead-free process per TI's standard qualification and is marked with appropriate package-level compliance indicators; full environmental compliance documentation is available in TI's official product change notices and material declarations.
TPS54354PWP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™
- Package/Case:
- 16-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 20V
- Voltage - Output (Min/Fixed):
- 1.8V
- Voltage - Output (Max):
- -
- Current - Output:
- 3A
- Frequency - Switching:
- 250kHz, 500kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-HTSSOP
TPS54354PWP FAQ
1.How can I place an order for TPS54354PWP through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54354PWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54354PWP reliable?
The price and inventory of TPS54354PWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54354PWP is usually 5 days.
3.What payment methods are accepted for TPS54354PWP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54354PWP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54354PWP?
TPS54354PWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54354PWP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54354PWP?
For technical support, including TPS54354PWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54354PWP requirements.
6.How does Aetrix verify that TPS54354PWP is sourced from the original manufacturer or authorized distributors?
All TPS54354PWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54354PWP meets industry standards.
7.What is the process for return or replacement of TPS54354PWP?
All TPS54354PWP units undergo pre-shipment inspection (PSI). If there is an issue with TPS54354PWP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54354PWP part is unused and in its original packaging.
Return procedure for TPS54354PWP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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