Texas Instruments TPS54372PWPG4
- Part No.:
- TPS54372PWPG4
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS54372PWPG4.pdf
- Description:
- IC REG CONV DDR 1OUT 20HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,059
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Product details
Overview
TPS54372PWPG4 from Texas Instruments is a 3-A synchronous buck PWM converter with integrated high- and low-side MOSFETs, designed for DDR memory termination and precision point-of-load regulation. It operates from 3 V to 6 V input, delivers 1.25 V output at up to 3 A continuous source/sink, features adjustable switching frequency (280–700 kHz), and includes tracking capability via REFIN pin (0.2–1.75 V range).
For engineers reviewing the TPS54372PWPG4 datasheet, TPS54372PWPG4 pinout, TPS54372PWPG4 application, or TPS54372PWPG4 equivalent, key selection considerations include its 60-mΩ high-side/low-side rDS(on), internal slow-start (2.6–4.1 ms), thermal shutdown (135–165°C), open-drain STATUS signal, and PowerPAD™ HTSSOP-20 package for enhanced thermal performance.
Technical Context
The TPS54372PWPG4 implements a voltage-mode PWM control architecture with a high-gain error amplifier (90–110 dB open-loop gain, 3–5 MHz unity-gain bandwidth) and adaptive dead-time logic to prevent shoot-through. Its oscillator supports fixed 350 kHz operation or externally set frequencies via RT-to-AGND resistor (68–180 kΩ), enabling optimization of efficiency vs. size trade-offs in high-density layouts.
It integrates dual 30-mΩ (typ.) N-channel MOSFETs, a 2.8-V internal bias regulator (VBIAS), undervoltage lockout (2.95 V start, 2.80 V stop), and cycle-by-cycle peak current limiting (4–7.5 A depending on VIN). The device supports bidirectional current flow-critical for active GTL/SSTL termination-and uses separate AGND and PGND pins to isolate noise-sensitive analog paths from high-current power loops.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.0 V to 6.0 V - Supports standard 3.3 V and 5 V system rails without external pre-regulation. |
| Continuous Output Current | ±3 A - Enables bidirectional sourcing and sinking for DDR VTT termination with no external components. |
| Switching Frequency | 280–700 kHz (adjustable) or 350 kHz (fixed) - Allows EMI tuning and inductor/capacitor size optimization. |
| High-Side rDS(on) | 59–88 mΩ (at 6 V VIN) - Minimizes conduction loss and improves full-load efficiency (>90% typical at 5 V in, 1.25 V out, 3 A). |
| Thermal Shutdown Threshold | 135–165°C - Protects against sustained overload; hysteresis of 10°C prevents thermal cycling. |
| REFIN Tracking Range | 0.2 V to 1.75 V - Enables precise ratio tracking (e.g., VTT = 0.5 × VDDQ) for DDR2/DDR3 applications. |
| STATUS Output Type | Open-drain - Allows wired-OR fault signaling and direct interface to microcontroller GPIO or system supervisor ICs. |
Pinout & Package
TPS54372PWPG4 is housed in a thermally enhanced 20-pin HTSSOP (PWP) PowerPAD™ package measuring 6.4 mm × 6.6 mm, with an exposed thermal pad soldered to AGND for efficient heat dissipation (θJA = 26.0°C/W with soldered pad).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND (Pin 1) | Analog ground reference | Return path for compensation network, VBIAS capacitor, RT resistor, and slow-start circuit; must be isolated from PGND except at single-point connection. |
| VSENSE (Pin 2) | Error amplifier inverting input | Connects to output voltage divider; senses regulated output for closed-loop control with ±0.03%/A load regulation. |
| COMP (Pin 3) | Error amplifier output | Drives external Type-2/Type-3 compensation network; 1.0–1.4 V/µs slew rate enables stable loop response up to 125 kHz crossover. |
| STATUS (Pin 4) | Open-drain fault indicator | Asserts low during UVLO, VBIAS underflow, or thermal shutdown; high-impedance when operational - used for system power sequencing. |
| BOOT (Pin 5) | Bootstrap supply node | Connects to 0.022–0.1 µF ceramic capacitor between BOOT and PH; generates floating gate drive for high-side MOSFET. |
| PH (Pins 6–10) | Phase node | Internal switch node connecting high-/low-side FETs and output inductor; requires low-inductance routing to minimize EMI and ringing. |
| RT (Pin 20) | Frequency setting input | Resistor to AGND sets switching frequency; 100 kΩ yields ~500 kHz - critical for optimizing efficiency vs. transient response. |
| ENA (Pin 19) | Enable control input | Logic-high (>1.2 V) enables operation; logic-low (<0.82 V) disables with <1.4 µA quiescent current - supports system-level power gating. |
| REFIN (Pin 18) | External tracking reference | High-impedance input (60–250 nA bias) accepting 0.2–1.75 V reference; overrides internal bandgap when valid - enables dynamic VTT adjustment. |
| VBIAS (Pin 17) | Internal bias regulator output | Supplies 2.7–2.9 V to internal circuitry; bypassed with 0.1–1.0 µF ceramic capacitor to AGND - also usable as external analog reference. |
| VIN (Pins 14–16) | Main power input | Supplies MOSFET switches and internal LDO; requires local 10 µF X5R/X7R ceramic bypass to PGND - minimizes input ripple and EMI. |
| PGND (Pins 11–13) | Power ground return | High-current return for low-side FET and input/output capacitors; must connect to large copper areas and avoid sharing traces with AGND. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 30-mΩ high-/low-side MOSFETs | Eliminates external power switches and reduces board area by >40% versus discrete solutions while maintaining 3-A bidirectional capability. |
| Adjustable 280–700 kHz switching frequency | Enables layout optimization: higher frequencies allow smaller inductors/capacitors; lower frequencies improve light-load efficiency and reduce EMI. |
| 6%–90% VI output tracking range | Supports precise VTT generation across DDR voltage standards (e.g., 1.25 V for DDR2, 0.75 V for DDR3) using simple resistor dividers on REFIN. |
| Separate AGND and PGND pins | Prevents ground noise coupling into error amplifier and compensation network - essential for sub-1% output regulation accuracy under dynamic loads. |
| Internal slow-start (2.6–4.1 ms) | Controls output ramp rate to limit inrush current during power-up, preventing input rail collapse and ensuring reliable system boot sequencing. |
| Thermal shutdown with 10°C hysteresis | Provides fail-safe protection during sustained overloads or poor heatsinking; automatic recovery avoids manual reset requirements. |
Applications
| DDR Memory Termination Voltage | Active Termination of GTL/SSTL Logic |
|---|---|
Use Scenario: Providing matched termination voltage (VTT) for DDR2/DDR3 memory buses in servers and workstations. IC Role / Device Role / Timing Role: Precision-tracking buck converter sourcing/sinking up to ±3 A to maintain VTT = 0.5 × VDDQ with <0.03%/A load regulation. Use Value: Eliminates need for external op-amps or discrete FETs, reducing BOM count and improving termination accuracy under fast load transients (0–2.25 A in 25 ms). |
Use Scenario: Active bus termination for high-speed GTL+ and SSTL-2 interfaces in telecom backplanes and FPGA I/O banks. IC Role / Device Role / Timing Role: Bidirectional current sink/source regulator maintaining stable termination voltage despite rapid bus state changes. Use Value: Achieves <50 mV output ripple at 700 kHz switching and supports 1.25 V @ 3 A with <1.253 V – 1.247 V load regulation - critical for signal integrity at >200 MHz data rates. |
| DAC-Controlled High-Current Output Stage | Precision Point-of-Load Power Supply |
Use Scenario: Programmable current/voltage source in test equipment and programmable power supplies. IC Role / Device Role / Timing Role: Tracking regulator whose REFIN pin accepts DAC output (0.2–1.75 V) to dynamically adjust VTT or VDDQ-derived rails. Use Value: Enables real-time voltage margining and calibration without hardware changes; 0.25 V/ms slow-start ensures controlled ramping during DAC updates. |
Use Scenario: Local regulation for ASICs, FPGAs, or DSPs requiring tight-tolerance, low-noise 1.2–1.8 V supplies. IC Role / Device Role / Timing Role: High-bandwidth (up to 125 kHz crossover) synchronous buck delivering ±3 A with 90–95% efficiency at 5 V input. Use Value: Delivers <50 mVpp output ripple and <50 mV transient deviation (0–2.25 A step) - meets stringent noise requirements for RF and mixed-signal SoCs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54373PWPR | Same PWP package and pinout; differs only in tape-and-reel packaging (R suffix) and RoHS compliance - identical electrical specs and thermal performance. | No functional difference; suitable for automated assembly where reel packaging is required. | Select TPS54373PWPR only when volume production demands tape-and-reel delivery; otherwise TPS54372PWPG4 is functionally identical. |
| TPS543B20RVFT | 4-A, 2.95–16 V input, 3.3-MHz D-CAP3 control; QFN-17 package; no REFIN tracking input; higher VIN range and bandwidth but lacks bidirectional current capability. | Targets higher-input industrial systems; not suitable for DDR VTT due to missing tracking and sink-only operation. | Choose TPS543B20RVFT only for non-tracking, higher-VIN (>6 V), higher-frequency applications; not a drop-in replacement for TPS54372PWPG4 DDR use cases. |
Compared with TPS54372PWPG4, TPS54373PWPR offers identical functionality in reel format for SMT lines, while TPS543B20RVFT provides higher input voltage and switching speed but sacrifices REFIN-based tracking and bidirectional current - making it unsuitable for DDR termination where those features are mandatory.
Availability
TPS54372PWPG4 is available at Aetrix Electronics and suitable for DDR memory subsystems, high-speed logic termination circuits, and precision point-of-load regulators requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for TPS54372PWPG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion and system power architecture.
The TPS54372PWPG4 belongs to TI's SWIFT™ family of integrated power converters, engineered specifically for high-current, low-voltage tracking and termination applications in memory interfaces and high-speed digital systems.
FAQ
What is the maximum continuous output current capability of the TPS54372PWPG4?
The TPS54372PWPG4 supports ±3 A continuous output current - meaning it can both source and sink up to 3 A. This bidirectional capability is essential for DDR memory termination where current flows into or out of the VTT rail depending on bus state. Performance is validated across the full operating temperature range (–40°C to 125°C junction) and input voltage range (3 V to 6 V), with thermal shutdown protecting against sustained overload conditions.
Does the TPS54372PWPG4 support external frequency adjustment, and how is it configured?
Yes, the TPS54372PWPG4 supports externally adjustable switching frequency from 280 kHz to 700 kHz using a resistor connected between the RT pin (Pin 20) and AGND. A 100 kΩ resistor sets ~500 kHz, 68 kΩ yields ~700 kHz, and 180 kΩ gives ~280 kHz. Leaving RT floating selects the internal default of 350 kHz. The TPS54372PWPG4 datasheet provides the exact calculation formula and tolerance guidance for resistor selection based on desired frequency accuracy.
How does the REFIN pin enable tracking functionality in the TPS54372PWPG4?
The REFIN pin (Pin 18) of the TPS54372PWPG4 accepts an external reference voltage from 0.2 V to 1.75 V, allowing precise output tracking - for example, setting VTT = 0.5 × VDDQ in DDR systems. When a valid REFIN voltage is applied, it overrides the internal 0.6-V bandgap reference. The TPS54372PWPG4 regulates VSENSE to match REFIN, enabling accurate ratio-based outputs without additional op-amps or feedback resistors.
What thermal management features does the TPS54372PWPG4 include, and how is the PowerPAD™ used?
The TPS54372PWPG4 incorporates thermal shutdown (trip point 135–165°C, 10°C hysteresis) and is packaged in a 20-pin HTSSOP (PWP) with an exposed PowerPAD™ thermal pad. This pad must be soldered directly to a dedicated AGND copper plane on the PCB, using at least six 0.013-inch vias to internal ground layers. With proper layout, thermal impedance drops to 26.0°C/W, enabling 3.85 W power dissipation at 25°C ambient - critical for maintaining reliability at full 3-A load.
Can the TPS54372PWPG4 be used in applications requiring both sourcing and sinking current simultaneously?
Yes, the TPS54372PWPG4 is explicitly designed for bidirectional current operation - it can source up to 3 A to the output and sink up to 3 A from the output, making it ideal for active termination where current direction reverses rapidly (e.g., DDR VTT). Its synchronous buck architecture with matched high-/low-side MOSFETs and dedicated PH node routing supports seamless transitions between sourcing and sinking modes without external components or control logic.
TPS54372PWPG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™
- Package/Case:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Applications:
- Converter, DDR
- Voltage - Input:
- 3V ~ 6V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.2V ~ 4.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-HTSSOP
TPS54372PWPG4 FAQ
1.How can I place an order for TPS54372PWPG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54372PWPG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54372PWPG4 reliable?
The price and inventory of TPS54372PWPG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54372PWPG4 is usually 5 days.
3.What payment methods are accepted for TPS54372PWPG4?
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4.How is shipping managed for TPS54372PWPG4?
TPS54372PWPG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54372PWPG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54372PWPG4?
For technical support, including TPS54372PWPG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54372PWPG4 requirements.
6.How does Aetrix verify that TPS54372PWPG4 is sourced from the original manufacturer or authorized distributors?
All TPS54372PWPG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54372PWPG4 meets industry standards.
7.What is the process for return or replacement of TPS54372PWPG4?
All TPS54372PWPG4 units undergo pre-shipment inspection (PSI). If there is an issue with TPS54372PWPG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54372PWPG4 part is unused and in its original packaging.
Return procedure for TPS54372PWPG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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