Texas Instruments TPS54395RSAR
- Part No.:
- TPS54395RSAR
- Manufacturer:
- Texas Instruments
- Package:
- 16-VQFN Exposed Pad
- Datasheet:
-
TPS54395RSAR.pdf
- Description:
- IC REG BUCK ADJ 3A DL 16QFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,057
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Product details
Overview
TPS54395RSAR from Texas Instruments is a dual-channel synchronous step-down DC/DC converter with integrated 90 mΩ high-side and 60 mΩ low-side N-channel MOSFETs per channel, supporting 3 A continuous output current per channel, 4.5 V to 18 V input range, 0.76 V to 7.0 V adjustable output voltage, and 700 kHz pseudo-fixed switching frequency. It delivers point-of-load regulation for digital TV power supplies and networking home terminals.
For engineers reviewing the TPS54395RSAR datasheet, TPS54395RSAR pinout, TPS54395RSAR application, or TPS54395RSAR equivalent, key selection factors include D-CAP2™ adaptive on-time control for fast transient response without external compensation, non-sinking pre-biased soft start, Eco-mode™ operation for light-load efficiency, and thermal shutdown with hiccup protection.
Technical Context
The TPS54395RSAR implements dual independent D-CAP2™ control loops-each combining adaptive on-time PWM with internal ramp-based ripple emulation to enable stable operation with ceramic or ultra-low-ESR output capacitors. Its valley-current sensing uses temperature-compensated rDS(on) loss-less detection on the low-side FETs.
Each channel features independent enable (EN1/EN2), soft-start (SS1/SS2), feedback (VFB1/VFB2), and bootstrap (VBST1/VBST2) inputs, with shared signal ground (GND) and dedicated power grounds (PGND1/PGND2). The VREG5 5.5 V LDO powers internal circuitry and supports external biasing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 18 V - supports wide industrial and consumer input rails including 5 V, 12 V, and 15 V systems. |
| Output Current (per channel) | 3 A continuous - enables dual-rail PoL conversion for SoC core and I/O domains without derating. |
| Switching Frequency | 700 kHz (pseudo-fixed) - balances EMI performance, inductor size, and efficiency across input/output combinations. |
| Feedback Reference Voltage | 765 mV ±7 mV - sets output voltage via resistor divider; enables precise 1.5 V, 3.3 V, and other common logic rails. |
| High-Side rDS(on) | 90 mΩ @ 25°C - minimizes conduction loss at high duty cycles; thermally compensated for consistent OCP accuracy. |
| Low-Side rDS(on) | 60 mΩ @ 25°C - enables loss-less current sensing and reduces heat generation during CCM operation. |
| Soft-Start Charge Current | –8.0 µA (typ) - allows programmable startup time using external SSx-to-GND capacitor; prevents inrush current. |
| Thermal Shutdown Threshold | 155°C (typ) with 25°C hysteresis - protects against sustained overload; junction temperature recovery enables automatic restart. |
Pinout & Package
TPS54395RSAR is housed in a 4 mm × 4 mm, 16-pin VQFN package (RSA) with exposed thermal pad (PowerPAD™) that must be soldered to PCB ground for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1 / VIN2 | Power Input | Independent input rails for each buck channel; accepts 4.5–18 V; connects to high-side FET drains and VREG5 LDO input. |
| VBST1 / VBST2 | Bootstrap Supply | Drives high-side gate; requires 0.1 µF ceramic capacitor to respective SWx pin; supports >5.7 V differential over SWx. |
| SW1 / SW2 | Switch Node | Drain-source connection point of both FETs per channel; carries high di/dt; routing impacts EMI and efficiency. |
| PGND1 / PGND2 | Power Ground | Low-side FET source return; separate paths minimize noise coupling between channels; connects to current sense node. |
| EN1 / EN2 | Enable Control | Logic-level inputs (2.0 V H-threshold, 0.4 V L-threshold); enable/disable each channel independently; 450 kΩ internal pull-down. |
| SS1 / SS2 | Soft-Start | Current-sink outputs (–8 µA typ); capacitor to GND sets ramp time; supports non-sinking pre-biased startup. |
| VFB1 / VFB2 | Feedback Input | Monitors output voltage via resistor divider; 765 mV reference; ±0.4 µA input bias enables high-impedance dividers. |
| GND | Signal Ground | Reference for SSx, VFBx, and logic circuits; must tie to PGND at single-point star ground to avoid noise injection. |
| VREG5 | Internal LDO Output | 5.5 V regulated supply for internal circuitry; bypass with ≥1 µF ceramic; powers VBSTx charge pump when enabled. |
| Exposed Pad | Thermal & Electrical Ground | Must be soldered to solid GND plane with ≥4 thermal vias; primary path for heat dissipation and low-impedance return. |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP2™ Control Mode | Eliminates external compensation components and enables stable operation with ceramic or POSCAP output capacitors while delivering sub-10 µs load transient response. |
| Auto-Skip Eco-mode™ | Automatically transitions from PWM to pulse-skipping at light loads (<300 mA), maintaining >85% efficiency down to 10 mA output current. |
| Non-Sinking Pre-Biased Soft Start | Prevents reverse current flow into pre-biased outputs by gradually enabling low-side FET conduction-critical for hot-swap and multi-rail sequencing. |
| Cycle-by-Cycle Over-Current Protection | Uses temperature-compensated rDS(on) sensing to maintain accurate 4.7 A (typ) current limit across –40°C to 85°C ambient without external sense resistors. |
| Hiccup-Mode Overload Recovery | Enters 7× soft-start delay after UVP detection (68% VREF), limiting average power dissipation during sustained short-circuit events and preventing thermal runaway. |
| Integrated 5.5 V VREG5 LDO | Provides clean, regulated bias for internal logic and gate drivers; eliminates need for external bias supply and simplifies system BOM. |
Applications
| Digital Television Power Supply | Networking Home Terminal |
|---|---|
Use Scenario: Powers SoC core (1.5 V), memory interface (3.3 V), and USB PHY (5 V) from a single 12 V input rail in compact set-top box designs. IC Role / Device Role / Timing Role: Dual-channel synchronous buck regulator delivering tightly regulated, low-noise DC rails with independent enable and soft-start sequencing. Use Value: Reduces component count by replacing two discrete converters; D-CAP2™ ensures <50 mV output deviation during 3 A load steps. | Use Scenario: Supplies FPGA I/O bank (3.3 V) and transceiver core (1.2 V) in residential gateway routers with strict thermal constraints. IC Role / Device Role / Timing Role: Dual-output PoL regulator with independent feedback and thermal monitoring per channel for mixed-voltage domain management. Use Value: Eco-mode™ sustains >90% efficiency at standby current (50 mA), extending system uptime in always-on applications. |
| Digital Set-Top Box (STB) | Gaming Console Subsystem |
Use Scenario: Generates 1.2 V CPU core and 1.8 V video decoder rails from 5 V or 12 V input in space-constrained STB mainboards. IC Role / Device Role / Timing Role: Dual synchronous buck controller with pre-biased soft start enabling safe hot-plug operation of daughterboards. Use Value: Non-sinking startup prevents bus droop during field firmware updates; thermal shutdown protects against enclosure overheating. | Use Scenario: Provides auxiliary 3.3 V and 5 V rails for audio codec, Wi-Fi module, and sensor hub in handheld gaming devices. IC Role / Device Role / Timing Role: Compact dual buck converter with VQFN thermal pad enabling direct PCB heatsinking in fanless enclosures. Use Value: 4 mm × 4 mm RSA package saves >30% board area vs. two discrete 3 A converters; PowerPAD™ lowers θJA to 32.8°C/W. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54394RSAR | Same pinout and package; lower 2.5 A per channel rating; identical D-CAP2™ control and Eco-mode™. | Suitable for lower-power applications where 3 A headroom is unnecessary; reduced thermal stress at same layout. | Select when total solution cost or thermal margin is prioritized over peak current capability. |
| MP2451DT-LF-Z | Single-channel 3 A converter; no dual output or VREG5 LDO; requires external compensation; 2 MHz fixed frequency. | Requires two ICs to match dual-rail functionality; higher EMI due to 2 MHz switching; no pre-biased soft start. | Choose only if higher frequency is mandatory and board area is less constrained than BOM count or sequencing complexity. |
Compared with TPS54394RSAR, the TPS54395RSAR provides 20% higher per-channel current capacity and identical feature set; versus MP2451DT-LF-Z, it delivers integrated dual-channel operation, simplified design, and superior transient performance without external compensation.
Availability
TPS54395RSAR is available at Aetrix Electronics and suitable for digital television power supplies, networking home terminals, and digital set-top box (STB) applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for TPS54395RSAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management IC design and manufacturing.
The TPS54395 belongs to TI's D-CAP2™ synchronous buck converter product line, engineered for high-efficiency, low-component-count point-of-load regulation in space- and thermal-constrained consumer and industrial systems.
FAQ
What is the recommended input capacitor configuration for TPS54395RSAR?
TPS54395RSAR requires a minimum 10 µF ceramic input capacitor rated for >20 V, plus 0.1 µF X5R/X7R ceramics placed directly at VIN1 and VIN2 pins to suppress high-frequency SW node ringing. Bulk capacitance beyond 10 µF may be added based on hold-up time requirements, but the 0.1 µF local caps are mandatory for stability and EMI control in the TPS54395RSAR design.
Does TPS54395RSAR support pre-biased output startup?
Yes, TPS54395RSAR implements non-sinking pre-biased soft start. When the output voltage is already present at startup, the controller delays full low-side FET activation and incrementally increases conduction time cycle-by-cycle, preventing reverse current flow and ensuring monotonic ramp-up of VO1 and VO2 without droop or overshoot.
What is the function of the VREG5 pin on TPS54395RSAR?
The VREG5 pin on TPS54395RSAR outputs a regulated 5.5 V supply used internally to power gate drivers and control logic. It must be bypassed with ≥1 µF ceramic capacitor to GND. VREG5 also feeds the internal charge pump for VBST1/VBST2, eliminating need for external bias supplies in the TPS54395RSAR application.
How does the D-CAP2™ control mode improve transient response in TPS54395RSAR?
D-CAP2™ control in TPS54395RSAR uses an internal ramp to emulate output ripple, enabling immediate on-time adjustment in response to load steps without waiting for error amplifier settling. This achieves <10 µs recovery time for 3 A load transients-up to 5× faster than conventional voltage-mode controllers-and eliminates need for external compensation networks.
Can TPS54395RSAR operate with ceramic output capacitors?
Yes, TPS54395RSAR is explicitly designed for ceramic and ultra-low-ESR output capacitors. D-CAP2™ control compensates for near-zero ESR by injecting synthetic ripple, ensuring loop stability even with 20–68 µF X5R/X7R ceramics-no additional ESR or feed-forward capacitors required for basic operation.
TPS54395RSAR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP2™, Eco-Mode™
- Package/Case:
- 16-VQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 18V
- Voltage - Output (Min/Fixed):
- 0.76V
- Voltage - Output (Max):
- 7V
- Current - Output:
- 3A
- Frequency - Switching:
- 700kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QFN (4x4)
TPS54395RSAR FAQ
1.How can I place an order for TPS54395RSAR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54395RSAR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54395RSAR reliable?
The price and inventory of TPS54395RSAR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54395RSAR is usually 5 days.
3.What payment methods are accepted for TPS54395RSAR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54395RSAR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54395RSAR?
TPS54395RSAR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54395RSAR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54395RSAR?
For technical support, including TPS54395RSAR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54395RSAR requirements.
6.How does Aetrix verify that TPS54395RSAR is sourced from the original manufacturer or authorized distributors?
All TPS54395RSAR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54395RSAR meets industry standards.
7.What is the process for return or replacement of TPS54395RSAR?
All TPS54395RSAR units undergo pre-shipment inspection (PSI). If there is an issue with TPS54395RSAR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54395RSAR part is unused and in its original packaging.
Return procedure for TPS54395RSAR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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