Texas Instruments TPS54418RTET
- Part No.:
- TPS54418RTET
- Manufacturer:
- Texas Instruments
- Package:
- 16-WFQFN Exposed Pad
- Datasheet:
-
TPS54418RTET.pdf
- Description:
- IC REG BUCK ADJ 4A 16WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:331
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS54418RTET from Texas Instruments is a 2.95-V to 6-V input, 4-A synchronous step-down DC/DC converter with integrated 30-mΩ high- and low-side MOSFETs, 2-MHz switching frequency capability, ±1% voltage reference accuracy over –40°C to 150°C, and thermally enhanced 3 mm × 3 mm WQFN-16 package. It delivers point-of-load regulation for FPGAs and microprocessors with soft-start control, power-good monitoring, and cycle-by-cycle current limiting.
For engineers reviewing the TPS54418RTET datasheet, TPS54418RTET pinout, TPS54418RTET application, or TPS54418RTET equivalent, key selection considerations include its 4-A continuous output current, 350-μA quiescent current in active operation, 2-μA shutdown current, adjustable UVLO via EN pin, and compatibility with external clock synchronization at 300–2000 kHz.
Technical Context
The TPS54418RTET implements constant-frequency peak-current-mode control with internal slope compensation to prevent subharmonic oscillation across duty cycles up to 100%. Its transconductance error amplifier (225 μS normal / 70 μS soft-start mode) compares VSENSE against either the 0.8-V reference or SS voltage, enabling precise regulation and controlled startup.
It features a PLL-based RT/CLK interface supporting both resistor-programmed timing (200–2000 kHz) and external clock synchronization (300–2000 kHz), plus BOOT-PH UVLO protection that sustains high-side conduction until BOOT voltage drops below 2.5 V-enabling near-100% duty cycle operation during dropout conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.95 V to 6 V - supports single-cell Li-ion, 3.3-V, and 5-V rails without pre-regulation. |
| Output Current | 4 A continuous - sufficient for core power of mid-tier FPGAs and DSPs. |
| Switching Frequency | 200 kHz to 2 MHz - enables compact magnetics and optimized efficiency vs. size trade-offs. |
| Voltage Reference Accuracy | 0.8 V ±1% over –40°C to 150°C - ensures stable output regulation under thermal stress. |
| Quiescent Current | 350 μA typical - minimizes no-load power loss in always-on systems. |
| Shutdown Current | 2 μA - enables ultra-low-power system sleep modes. |
| MOSFET RDS(on) | 30 mΩ high-side / 30 mΩ low-side (typ.) - reduces conduction losses at 4-A load. |
| Power-Good Threshold | 93% to 107% of nominal VOUT - provides reliable sequencing and fault detection. |
Pinout & Package
TPS54418RTET uses a thermally enhanced 3 mm × 3 mm, 16-pin WQFN package with exposed PowerPad (GND-connected) for optimal thermal performance. The package is RoHS-compliant and moisture-sensitive level 2a per J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pins 1, 2, 16) | Input supply connection | Accepts 2.95–6 V; multiple pins reduce trace resistance and improve current handling. |
| GND (Pins 3, 12) | Power ground return | Low-inductance path for high di/dt switching currents; connects directly to PowerPad. |
| PH (Pin 10) | Switch node | Drain of low-side MOSFET / source of high-side MOSFET; critical for EMI layout and boot capacitor placement. |
| BOOT (Pin 13) | High-side gate drive supply | Requires 0.1-μF X7R/X5R ceramic capacitor to PH; UVLO disables high-side if BOOT–PH < 2.5 V. |
| VSENSE (Pin 6) | Feedback input | Inverting input of error amplifier; sets output voltage via resistor divider to 0.8 V reference. |
| COMP (Pin 7) | Error amplifier output | Connects to RC compensation network; drives PWM comparator with 225-μS transconductance. |
| EN (Pin 15) | Enable control | Pull <1.18 V to disable; internal 0.6-μA pull-up allows floating-enable; supports UVLO adjustment with resistors. |
| SS (Pin 9) | Soft-start timing | 1.8-μA internal current source charges external capacitor; controls output ramp rate and enables sequencing. |
| PWRGD (Pin 14) | Open-drain power-good | Asserts low when VOUT is outside 93–107% window; requires external pull-up for logic-level signaling. |
| RT/CLK (Pin 8) | Frequency programming/sync | Configurable as resistor-to-GND (200–2000 kHz) or external clock input (300–2000 kHz) with PLL lock-in. |
| AGND (Pin 5) | Analog ground | Separate ground for sensitive analog circuitry; must be tied to GND near device with short trace. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 30-mΩ MOSFETs | Enables high-efficiency 4-A conversion without external switches, reducing BOM count and layout complexity. |
| Adjustable soft-start | External capacitor on SS pin provides programmable output ramp time, preventing inrush current and enabling power sequencing. |
| Synchronization capability | RT/CLK pin supports external clock locking (300–2000 kHz), allowing noise-sensitive systems to avoid frequency beating. |
| Pre-biased start-up | Safe turn-on into precharged output capacitors without reverse current flow or output voltage overshoot. |
| Comprehensive protection | Includes cycle-by-cycle current limit, thermal shutdown (175°C), frequency foldback, and UV/OV PWRGD fault reporting. |
Applications
| Point-of-Load FPGA Core Supply | Industrial PLC I/O Module Regulator |
|---|---|
|
Use Scenario: Powers 1.2-V core rail of Xilinx Artix-7 FPGA in a space-constrained industrial controller. IC Role / Device Role / Timing Role: Primary synchronous buck regulator delivering 4-A continuous current with tight transient response. Use Value: Integrated MOSFETs and 2-MHz capability allow use of 1-μH inductor and <1000-μF output capacitance, reducing board area by >35% vs. discrete solutions. |
Use Scenario: Generates isolated 3.3-V supply for digital I/O conditioning circuits in DIN-rail mounted PLCs. IC Role / Device Role / Timing Role: Main DC/DC converter operating from 5-V backplane with EN-controlled sequencing and PWRGD status reporting. Use Value: 2-μA shutdown current and –40°C to 150°C junction rating ensure reliable operation in unventilated enclosures with wide ambient swings. |
| Optical Transceiver Bias Supply | Automotive ADAS Camera Power |
|
Use Scenario: Provides low-noise 2.5-V bias for laser driver ICs in 10G SFP+ modules. IC Role / Device Role / Timing Role: Secondary regulated supply synchronized to system clock via RT/CLK to minimize spectral interference. Use Value: 200-kHz to 2-MHz programmability enables EMI filtering at fixed frequencies away from data lanes, meeting Class B CISPR-32 limits. |
Use Scenario: Supplies 1.8-V core voltage to image signal processor (ISP) in rear-view camera ECU. IC Role / Device Role / Timing Role: High-reliability buck converter with thermal shutdown, PWRGD monitoring, and automotive-grade qualification support. Use Value: ±1% reference accuracy and 150°C max junction temperature meet AEC-Q100 Grade 2 requirements for under-hood vision systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54318RTET | 3-A output rating, identical pinout and feature set except reduced current capability and slightly higher RDS(on) (35 mΩ). | Suitable for lower-power FPGAs or microcontrollers where 4-A headroom is unnecessary. | Select when cost optimization is prioritized and full 4-A load is not required; shares same PCB footprint. |
| MP2315DJ-LF-Z | 4-A rated, 2.5–5.5 V input, 500-kHz fixed frequency, no RT/CLK sync, no PWRGD, smaller 2 mm × 2 mm QFN-8 package. | Better suited for consumer IoT devices where size and cost outweigh synchronization and monitoring needs. | Choose for space-constrained designs lacking clock sync requirements; verify thermal margin due to smaller thermal pad. |
Compared with TPS54418RTET, TPS54318RTET offers pin-compatible down-rating for cost-sensitive 3-A applications, while MP2315DJ-LF-Z trades synchronization, PWRGD, and thermal robustness for minimal footprint-making each viable only within their validated operational boundaries.
Availability
TPS54418RTET is available at Aetrix Electronics and suitable for FPGA power delivery, industrial PLCs, optical transceiver biasing, and automotive ADAS camera systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for TPS54418RTET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management IC design and manufacturing.
The TPS54418RTET belongs to TI's SWIFT™ synchronous buck converter family, engineered for high-density, high-efficiency point-of-load regulation in FPGA, ASIC, and microprocessor applications demanding precision, reliability, and thermal resilience.
FAQ
What is the maximum continuous output current of the TPS54418RTET?
The TPS54418RTET delivers 4 A continuous output current under recommended operating conditions (TJ ≤ 125°C, proper PCB thermal design). This rating assumes use of the 3 mm × 3 mm WQFN package with adequate copper area and thermal vias under the PowerPad. Derating applies above 125°C junction temperature per the thermal characteristics table in the datasheet.
Does the TPS54418RTET support external clock synchronization?
Yes, the TPS54418RTET supports external clock synchronization via the RT/CLK pin. When driven with a clean CMOS clock signal between 300 kHz and 2 MHz, the internal PLL locks to the falling edge of the input clock, enabling deterministic switching alignment for EMI reduction. The pin also accepts a timing resistor for free-running operation from 200 kHz to 2 MHz.
How is the output voltage set on the TPS54418RTET?
The output voltage of the TPS54418RTET is set using a resistor divider from VOUT to the VSENSE pin, referenced to an internal 0.8-V ±1% bandgap. For example, a 100-kΩ top resistor (R1) and 100-kΩ bottom resistor (R2) yields 1.6 V output. TI recommends 1% tolerance or better resistors and cautions against excessively large values (>1 MΩ) due to VSENSE input current errors.
What protection features does the TPS54418RTET include?
The TPS54418RTET integrates cycle-by-cycle current limiting, thermal shutdown at 175°C with 15°C hysteresis, BOOT-PH UVLO, undervoltage lockout on VIN (2.6 V default), overvoltage protection via PWRGD comparator activation, and frequency foldback during overload. These features collectively prevent damage during startup, short-circuit, or thermal overload events without requiring external components.
Can the TPS54418RTET start up into a pre-biased output?
Yes, the TPS54418RTET supports safe start-up into a pre-biased output. Its control architecture prevents reverse current flow through the low-side MOSFET during initial soft-start, eliminating output voltage undershoot or latch-up. This behavior is confirmed in the datasheet's "Safe Start-Up into Prebiased Output" section and verified across –40°C to 125°C operating range.
TPS54418RTET Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™
- Package/Case:
- 16-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 0.803V
- Voltage - Output (Max):
- 4.5V
- Current - Output:
- 4A
- Frequency - Switching:
- 200kHz ~ 2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WQFN (3x3)
TPS54418RTET FAQ
1.How can I place an order for TPS54418RTET through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54418RTET on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54418RTET reliable?
The price and inventory of TPS54418RTET are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54418RTET is usually 5 days.
3.What payment methods are accepted for TPS54418RTET?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54418RTET transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54418RTET?
TPS54418RTET orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54418RTET order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54418RTET?
For technical support, including TPS54418RTET datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54418RTET requirements.
6.How does Aetrix verify that TPS54418RTET is sourced from the original manufacturer or authorized distributors?
All TPS54418RTET products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54418RTET meets industry standards.
7.What is the process for return or replacement of TPS54418RTET?
All TPS54418RTET units undergo pre-shipment inspection (PSI). If there is an issue with TPS54418RTET, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54418RTET part is unused and in its original packaging.
Return procedure for TPS54418RTET:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS54418RTET Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
