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Texas Instruments TPS54495RSAR
- Part No.:
- TPS54495RSAR
- Manufacturer:
- Texas Instruments
- Package:
- 16-VQFN Exposed Pad
- Datasheet:
-
TPS54495RSAR.pdf
- Description:
- IC REG BUCK ADJ 4A/2A DL 16QFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,089
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Product details
Overview
TPS54495RSAR from Texas Instruments is a dual-channel synchronous step-down DC/DC converter with integrated 90 mΩ high-side and 60 mΩ low-side N-channel MOSFETs per channel, delivering 4 A on Channel 1 and 2 A on Channel 2. It operates across 4.5 V–18 V input, supports 0.76 V–7 V output, and uses D-CAP2™ adaptive on-time control for fast transient response in point-of-load regulation for digital TV, STB, and gaming console power supplies.
For engineers reviewing the TPS54495RSAR datasheet, TPS54495RSAR pinout, TPS54495RSAR application, or TPS54495RSAR equivalent, key selection criteria include its 700 kHz pseudo-fixed switching frequency, non-sinking pre-biased soft start, thermally compensated cycle-by-cycle over-current protection, Eco-mode™ light-load efficiency, and HTSSOP-16 PowerPAD™ package thermal performance.
Technical Context
The TPS54495RSAR implements dual independent D-CAP2™ control loops-each combining adaptive on-time PWM with internal ramp compensation to enable stable operation with ceramic or ultra-low-ESR output capacitors without external loop compensation. Its valley-current sensing uses temperature-compensated rDS(on) loss-less detection on the low-side FET.
Each channel features autonomous soft-start via dedicated SS1/SS2 pins (8 µA charge current), independent EN1/EN2 logic enables, and separate VBST1/VBST2 bootstrap supplies with internal diodes tied to VREG5. Protection includes hiccup-mode OCP, UVLO on VREG5, UVP/OVP at 68%–73% of reference, and thermal shutdown at 155°C with 25°C hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 18 V - supports wide industrial and consumer DC bus inputs including 5 V, 12 V, and 18 V rails. |
| Output Current Capability | CH1: 4 A continuous, CH2: 2 A continuous - enables independent high-efficiency POL for core and I/O rails. |
| Switching Frequency | ~700 kHz (adaptive on-time) - balances EMI, size, and efficiency; frequency varies <±5% with VIN and VOUT. |
| Feedback Reference Voltage | 765 mV ±7 mV (25°C), ±115 ppm/°C TC - sets precise output voltage via resistor divider; enables 0.76 V–7 V range. |
| High-Side rDS(on) | 90 mΩ (25°C) - minimizes conduction loss at high duty cycles; thermally compensated for consistent current limit. |
| Low-Side rDS(on) | 60 mΩ - enables loss-less current sensing and efficient synchronous rectification down to zero load. |
| Soft-Start Charge Current | –8.0 µA (typ) on SS1/SS2 - allows adjustable startup time via external capacitor; supports non-sinking pre-biased startup. |
| Thermal Shutdown Threshold | 155°C (typ), 25°C hysteresis - protects against sustained overload; junction temp must stay <110°C during VREG5 ramp-up. |
Pinout & Package
TPS54495RSAR is housed in a 4 mm × 4 mm, 16-pin VQFN (RSA) package with exposed thermal pad (PowerPAD™) requiring solder connection to PCB ground plane for optimal thermal dissipation (θJCbot = 1.6°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1 (Pin 3) | Main input supply for Channel 1 | Connects to high-side FET drain and powers internal 5.5 V LDO (VREG5); requires local 10 µF + 0.1 µF decoupling. |
| VIN2 (Pin 2) | Main input supply for Channel 2 | Independent input rail; enables dual-input configurations or shared input with separate filtering. |
| VBST1 (Pin 4) | Bootstrap supply for CH1 high-side gate | Must be connected to SW1 via 0.1 µF X5R ceramic; internal diode ties to VREG5 for self-boot. |
| VBST2 (Pin 1) | Bootstrap supply for CH2 high-side gate | Same architecture as VBST1; isolated bootstrap paths prevent cross-talk between channels. |
| SW1 (Pin 5) | Channel 1 switch node | Connects high-side and low-side FETs; drives external inductor; requires tight layout to minimize ringing. |
| SW2 (Pin 16) | Channel 2 switch node | Independent switch node; enables separate LC filter design and layout isolation for noise-sensitive loads. |
| EN1 (Pin 7) | Enable control for Channel 1 | Active-high logic (2.0 V threshold); allows independent sequencing or power-gating of CH1. |
| EN2 (Pin 14) | Enable control for Channel 2 | Same logic threshold as EN1; supports staggered startup or fault-isolated shutdown. |
| VFB1 (Pin 9) | Feedback input for Channel 1 | Monitors output via resistor divider; 0.765 V reference enables accurate 3.3 V, 2.5 V, 1.8 V, etc., regulation. |
| VFB2 (Pin 12) | Feedback input for Channel 2 | Independent feedback path; allows different output voltages per channel (e.g., 3.3 V + 1.5 V). |
| GND (Pin 10) | Signal ground reference | Star-point return for VFBx, SSx, and sensitive analog circuitry; must be separated from PGND planes. |
| VREG5 (Pin 11) | 5.5 V linear regulator output | Powers internal circuitry and VBSTx; requires ≥1 µF ceramic bypass; active only when VIN1 > UVLO threshold. |
| SS1 (Pin 8) | Soft-start timing for Channel 1 | 8 µA constant-current sink; connect capacitor to GND to set ramp time (e.g., 100 nF → ~12.5 ms). |
| SS2 (Pin 13) | Soft-start timing for Channel 2 | Independent timing control; enables asymmetric startup sequences to avoid input inrush overlap. |
| PGND1 (Pin 6) | Power ground for CH1 low-side FET | Carries high di/dt return current; must route directly under SW1 and connect to thermal pad. |
| PGND2 (Pin 15) | Power ground for CH2 low-side FET | Separate return path prevents coupling between channels; connects to same thermal pad but distinct copper pour. |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP2™ Control Mode | Eliminates need for external compensation components while supporting ceramic, POSCAP, and SP-CAP output capacitors - reduces BOM count and layout area. |
| Auto-Skip Eco-mode™ | Enables >85% efficiency at 10 mA load (VIN=12 V, VOUT=3.3 V) by entering discontinuous conduction mode - extends battery life in standby states. |
| Non-Sinking Pre-Biased Soft Start | Prevents reverse current flow during startup into pre-charged outputs (e.g., hot-swap or rail-sharing systems) - avoids system-level brownouts. |
| Thermally Compensated OCP | Maintains constant 4.5–7.0 A CH1 and 2.8–5.0 A CH2 current limit across –40°C to 85°C ambient - ensures robust overload handling without derating. |
| Integrated Adaptive Gate Drivers | Optimizes high-side FET turn-on using VREG5-derived bootstrap and dynamic drive strength - reduces switching losses and improves light-load efficiency. |
| Hiccup-Mode Overload Protection | Limits junction temperature rise during sustained short-circuit by cycling 7× UVP enable delay (e.g., ~10.5 ms off-time) - prevents thermal runaway without latch-off. |
Applications
| Digital TV Power Supply | Networking Home Terminal |
|---|---|
Use Scenario: Powers SoC core (1.2 V/3 A), memory interface (1.5 V/2 A), and HDMI PHY (3.3 V/0.5 A) from 12 V DC input. IC Role / Device Role / Timing Role: Dual-channel POL regulator providing independent, sequenced, low-noise DC rails with fast load-transient response. Use Value: D-CAP2™ achieves <±15 mV output deviation during 0→4 A 1 µs load steps - eliminates need for large bulk capacitance. |
Use Scenario: Supplies CPU (1.1 V/2 A), DDR3 VTT (0.75 V/1.5 A), and USB controller (5 V/0.5 A via external LDO) in cable modem/router. IC Role / Device Role / Timing Role: Primary DC/DC converter generating tightly regulated, low-ripple intermediate rails for mixed-signal subsystems. Use Value: Non-sinking soft start prevents backfeed into powered-up DDR3 modules during cold boot - avoids data corruption. |
| Digital Set Top Box (STB) | Gaming Console Mainboard |
Use Scenario: Delivers 1.2 V/3 A to ARM processor and 3.3 V/1 A to tuner demodulator from 5 V or 12 V input in compact enclosure. IC Role / Device Role / Timing Role: High-density dual buck converter enabling single-package solution for multi-rail STB power tree. Use Value: 4 mm × 4 mm VQFN package with PowerPAD™ achieves 32.8°C/W θJA - sustains full load at 65°C ambient without airflow. |
Use Scenario: Generates GPU core (0.95 V/4 A) and I/O (1.8 V/2 A) rails in thermally constrained game console mainboard. IC Role / Device Role / Timing Role: Dual-phase capable POL regulator with independent EN/SS control for dynamic power-state transitions. Use Value: Independent EN1/EN2 allows GPU rail to enter deep sleep while I/O rail remains active - cuts system idle power by >40%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS544B20RVFT | 4 A/4 A dual-channel, 4.5–18 V input, 0.6–5.5 V output, PMBus-enabled, 750 kHz fixed frequency | Requires external compensation; supports telemetry and margining; larger 5 mm × 5 mm VQFN | Choose for systems needing digital monitoring, programmable margins, or matched 4 A/4 A capability. |
| MP8765GQ-Z | 4 A/2 A dual-channel, 4.5–18 V input, 0.6–7 V output, COT control, 650 kHz typical frequency | No integrated VREG5 LDO; no pre-biased soft start; lower thermal resistance (θJA = 26.5°C/W) | Choose for cost-sensitive designs where VREG5 is externally supplied and pre-bias immunity is not required. |
Compared with TPS54495RSAR, TPS544B20RVFT adds digital control but increases complexity and footprint, while MP8765GQ-Z reduces cost and improves thermal performance but removes critical analog features like non-sinking startup and integrated bias supply - making TPS54495RSAR optimal for analog-centric, space-constrained consumer POL designs.
Availability
TPS54495RSAR is available at Aetrix Electronics and suitable for digital TV, STB, and gaming console power supply designs requiring stable component supply, long-term production continuity, and automotive-grade reliability screening.
Supply support for TPS54495RSAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion.
The TPS54495RSAR belongs to TI's D-CAP2™ synchronous buck converter product line, engineered specifically for low-component-count, high-transient-response point-of-load regulation in space-constrained consumer electronics.
FAQ
What is the recommended input capacitor configuration for TPS54495RSAR?
TI specifies a minimum 10 µF ceramic bulk capacitor plus 0.1 µF ceramic capacitors placed directly between VIN1–PGND1 and VIN2–PGND2. The 0.1 µF caps reduce high-frequency switching noise at the SW nodes and improve stability. All capacitors must have voltage ratings exceeding the maximum input voltage (e.g., 25 V for 18 V max input). The TPS54495RSAR datasheet Figure 24 shows this configuration implemented with X5R dielectric parts.
Does TPS54495RSAR support independent voltage setting for each channel?
Yes, TPS54495RSAR supports fully independent output voltages via separate resistor dividers on VFB1 and VFB2. Each feedback pin references the same 765 mV internal bandgap, enabling precise settings such as 3.3 V on CH1 (R11 = 73.2 kΩ, R21 = 22.1 kΩ) and 1.5 V on CH2 (R12 = 21.5 kΩ, R22 = 22.1 kΩ), as validated in the datasheet design example.
How does the thermal pad on the TPS54495RSAR VQFN package affect PCB layout?
The exposed thermal pad on the TPS54495RSAR RSA package must be soldered to a solid GND copper pour with ≥4 thermal vias (0.3 mm diameter) connecting to inner-layer GND planes. TI's SLVSBH0A datasheet specifies this as mandatory for achieving θJCbot = 1.6°C/W and preventing thermal shutdown under full load. Failure to connect the pad degrades θJA by >20°C/W.
Can TPS54495RSAR operate with only one channel enabled?
Yes, TPS54495RSAR supports single-channel operation: tie EN2 to GND to disable Channel 2 while running Channel 1 at full 4 A. The disabled channel draws only 15–20 µA shutdown current (IVINSDN), and its VBST2, SW2, and PGND2 pins remain inactive. This mode is explicitly characterized in the Electrical Characteristics table and used in TI's typical efficiency curves.
What protection features are integrated into TPS54495RSAR?
TPS54495RSAR integrates cycle-by-cycle over-current protection (OCP) with thermally compensated rDS(on) sensing, hiccup-mode overload recovery, input UVLO on VREG5, output UVP/OVP at 68%–73% of reference, and thermal shutdown at 155°C with 25°C hysteresis. All protections are fully autonomous and require no external components - confirmed in Sections 7–9 of the SLVSBH0A datasheet.
TPS54495RSAR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP2™, Eco-Mode™
- Package/Case:
- 16-VQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 18V
- Voltage - Output (Min/Fixed):
- 0.76V
- Voltage - Output (Max):
- 7V
- Current - Output:
- 4A, 2A
- Frequency - Switching:
- 700kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QFN (4x4)
TPS54495RSAR FAQ
1.How can I place an order for TPS54495RSAR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54495RSAR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54495RSAR reliable?
The price and inventory of TPS54495RSAR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54495RSAR is usually 5 days.
3.What payment methods are accepted for TPS54495RSAR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54495RSAR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54495RSAR?
TPS54495RSAR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54495RSAR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54495RSAR?
For technical support, including TPS54495RSAR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54495RSAR requirements.
6.How does Aetrix verify that TPS54495RSAR is sourced from the original manufacturer or authorized distributors?
All TPS54495RSAR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54495RSAR meets industry standards.
7.What is the process for return or replacement of TPS54495RSAR?
All TPS54495RSAR units undergo pre-shipment inspection (PSI). If there is an issue with TPS54495RSAR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54495RSAR part is unused and in its original packaging.
Return procedure for TPS54495RSAR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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