My Inquiry
My Account
Texas Instruments TPS54617RUVR
- Part No.:
- TPS54617RUVR
- Manufacturer:
- Texas Instruments
- Package:
- 34-VFQFN Exposed Pad
- Datasheet:
-
TPS54617RUVR.pdf
- Description:
- IC REG BUCK ADJ 6A 34VQFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,848
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS54617RUVR from Texas Instruments is a 3-V to 6-V input, 6-A synchronous buck DC/DC converter with integrated 30-mΩ high- and low-side MOSFETs in a thermally enhanced 34-pin QFN (RUV) PowerPAD™ package. It delivers adjustable output down to 0.9 V with 1% reference accuracy and supports fixed or adjustable switching frequencies up to 1.6 MHz. It is used in point-of-load regulation for FPGAs and microprocessors requiring compact, high-efficiency power delivery.
For engineers reviewing the TPS54617RUVR datasheet, TPS54617RUVR pinout, TPS54617RUVR application, or TPS54617RUVR equivalent, key selection criteria include its 6-A continuous output capability, 3.5 mm × 7 mm footprint, thermal shutdown at 150°C, externally compensated loop for design flexibility, and synchronization support up to 1.6 MHz - all critical for high-density, thermally constrained embedded power systems.
Technical Context
The TPS54617RUVR implements a current-mode PWM control architecture with adaptive dead-time and leading-edge blanking (100 ns), enabling stable operation under fast load transients. Its error amplifier features 90–110 dB open-loop gain and 3–5 MHz unity-gain bandwidth, supporting Type-3 compensation networks for robust loop stability across wide input/output conditions.
It integrates dual MOSFETs with rDS(on) of 26–47 mΩ (high-side) and 36–65 mΩ (low-side) at 3 V input, and includes dedicated AGND/PGND separation, internal bias regulator (VBIAS = 2.70–2.90 V), and precision voltage reference (0.882–0.900 V) trimmed during manufacturing to ensure ±1% output accuracy over temperature and line/load variations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3 V to 6 V - compatible with standard 3.3 V and 5 V intermediate bus rails |
| Continuous Output Current | 6 A - sufficient for powering mid-range FPGAs, DSPs, and ASICs without external heatsinking |
| Output Voltage Accuracy | ±1% - achieved via factory-trimmed 0.891 V reference and precision error amplifier |
| Switching Frequency Range | 280 kHz to 1.6 MHz - adjustable via RT resistor or SYNC pin; enables optimization of size vs. efficiency |
| Thermal Shutdown Threshold | 135°C to 165°C - protects against sustained overload or poor PCB thermal design |
| Power MOSFET rDS(on) | 26–47 mΩ (HS), 36–65 mΩ (LS) - ensures >90% peak efficiency at 6 A with 3.3 V input |
| Package Thermal Resistance | 14.5°C/W (θJA), 0.5°C/W (θJC) - requires ≥12 thermal vias under PowerPAD for full 6-A operation |
Pinout & Package
TPS54617RUVR uses a 34-pin QFN (RUV) package with exposed thermal PowerPAD™ measuring 3.5 mm × 7 mm. The PowerPAD must be soldered to AGND on the PCB using ≥12 thermal vias for rated 6-A performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND (Pin 1) | Analog ground reference | Return for COMP, VSENSE, SS/ENA, SYNC, and VBIAS; must connect to PowerPAD |
| BOOT (Pin 5) | Bootstrap supply node | Drives high-side FET gate via 0.022–0.1 µF ceramic capacitor tied to PH |
| COMP (Pin 3) | Error amplifier output | Connects external Type-3 compensation network to VSENSE for loop stability |
| PGND (Pins 13–20, 30–34) | Power ground return | High-current return for MOSFETs and inductor; separate from AGND to minimize noise coupling |
| PH (Pins 6–12) | Phase node | Switching node connecting internal FETs to output inductor; requires minimal trace area |
| PWRGD (Pin 4) | Power-good indicator | Open-drain output active high when VSENSE ≥90% Vref; used for sequencing and fault signaling |
| RT (Pin 29) | Frequency setting input | Resistor to AGND sets fs from 280 kHz to 1.6 MHz; required for external sync or non-default frequency |
| SS/ENA (Pin 27) | Enable/slow-start control | Logic-enable threshold at 1.2 V; external capacitor extends soft-start time beyond internal 3.35 ms |
| SYNC (Pin 28) | Frequency synchronization | Accepts external clock (330–1600 kHz); selects internal 350/550 kHz when held low/high |
| VBIAS (Pin 26) | Bias regulator output | 2.70–2.90 V supply for internal circuitry; bypass with 0.1–1 µF ceramic to AGND |
| VIN (Pins 21–25) | Main input supply | 3–6 V input for power switches and VBIAS LDO; bypass with ≥10 µF ceramic near PGND |
| VSENSE (Pin 2) | Feedback input | Inverting input of error amplifier; connects to resistor divider from VOUT for adjustable regulation |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 30-mΩ MOSFETs | Enables 6-A continuous output in 3.5 mm × 7 mm footprint without external switches or drivers |
| Externally compensated error amplifier | Supports flexible Type-2 or Type-3 compensation for optimal transient response across varied L/C selections |
| Adjustable 280 kHz–1.6 MHz switching | Allows trade-off between inductor size (higher f) and conduction loss (lower f) in space-constrained designs |
| Dual ground system (AGND/PGND) | Reduces noise coupling between sensitive analog circuits and high-current power paths |
| Programmable slow-start via SS/ENA | Prevents inrush current by extending startup beyond internal 3.35 ms using external capacitor |
| Power-good (PWRGD) with hysteresis | Provides reliable reset signaling for processors and logic; 3% Vref hysteresis prevents chatter during marginal conditions |
Applications
| Point-of-Load FPGA Power | Industrial DSP Core Supply |
|---|---|
Use Scenario: Powers Xilinx Artix-7 or Intel Cyclone V FPGA core rail at 1.0–1.2 V, 4–6 A with tight voltage tolerance. IC Role / Device Role / Timing Role: Primary synchronous buck regulator delivering regulated core voltage; operates at 1.2 MHz to minimize inductor size. Use Value: Integrated FETs and 1% reference accuracy eliminate external components while meeting FPGA VCCINT ripple and sequencing requirements. |
Use Scenario: Supplies TI C6000 DSP core at 1.1 V, 5 A in motor control gateway with ambient temperatures up to 85°C. IC Role / Device Role / Timing Role: High-efficiency step-down converter with thermal shutdown protecting against overtemperature in sealed enclosures. Use Value: 0.5°C/W θJC enables direct thermal path to PCB ground plane, sustaining 6 A without heatsink in convection-cooled industrial environments. |
| Optical Transceiver Bias | Networking ASIC I/O Supply |
Use Scenario: Generates 3.3 V, 2.5 A bias for SFP+ optical module laser drivers and TIAs in 10G Ethernet line cards. IC Role / Device Role / Timing Role: Secondary buck regulator synchronized to system clock (via SYNC pin) to reduce EMI in dense backplane layouts. Use Value: 1.6 MHz sync capability aligns switching edges with system timing, minimizing spectral overlap with data lanes and easing EMC compliance. |
Use Scenario: Provides 1.8 V, 6 A supply to Broadcom BCM56xx switch ASIC I/O banks in enterprise switches. IC Role / Device Role / Timing Role: High-current POL regulator with PWRGD output sequenced to enable ASIC configuration after stable VDDIO. Use Value: Open-drain PWRGD with 90% Vref threshold and 3% hysteresis ensures clean, chatter-free reset assertion aligned to ASIC power-up timing specs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54610RUV | Same RUV package but fixed 350 kHz/550 kHz frequencies; no RT pin or SYNC capability | Lacks frequency adjustability and external sync; suitable only for cost-sensitive, fixed-frequency designs | Select TPS54610RUV if board layout rework is prohibited and 350/550 kHz meets EMI and size targets |
| MP2315DJ-LF-Z | Monolithic 6-A buck in 8-pin SOIC; 4.5–28 V input; no PG, no sync; lower integration (no VBIAS, no SS/ENA) | Higher input range but lacks power-good, soft-start, and sync - unsuitable for processor sequencing or noise-sensitive systems | Choose MP2315DJ-LF-Z only for simple 12 V intermediate bus conversion where sequencing and precision are not required |
Compared with TPS54617RUVR, TPS54610RUV sacrifices frequency flexibility for lower BOM count, while MP2315DJ-LF-Z trades feature completeness for wider input range and simpler layout - neither offers the same combination of 6-A capability, 1% accuracy, thermal management, and system-level control signals in the 3.5 mm × 7 mm RUV footprint.
Availability
TPS54617RUVR is available at Aetrix Electronics and suitable for FPGA power delivery, industrial DSP core supplies, and optical transceiver biasing requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for TPS54617RUVR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-reliability power conversion solutions.
The TPS54617RUVR belongs to TI's SWIFT™ family of synchronous buck regulators, designed specifically for high-density, low-voltage point-of-load applications in networking, computing, and industrial systems where thermal performance and design flexibility are critical.
FAQ
What is the maximum continuous output current of the TPS54617RUVR?
The TPS54617RUVR delivers 6 A continuous output current under recommended operating conditions (TJ ≤ 125°C, proper PCB thermal design). This rating assumes ≥12 thermal vias under the PowerPAD and a 3-inch × 3-inch 1-oz copper ground plane. At 6 A, peak efficiency exceeds 92% with 5 V input and 1.8 V output at 1.6 MHz.
Does the TPS54617RUVR require an external compensation network?
Yes, the TPS54617RUVR requires an external Type-2 or Type-3 compensation network connected between COMP and VSENSE pins. Its error amplifier is intentionally left uncompensated to provide design flexibility for optimizing transient response across different output inductors and capacitors - a key differentiator from fully integrated fixed-compensation regulators.
How is the switching frequency set on the TPS54617RUVR?
The TPS54617RUVR supports three frequency modes: fixed 350 kHz (SYNC ≤ 0.8 V), fixed 550 kHz (SYNC ≥ 2.5 V), or adjustable 280–1600 kHz via resistor from RT to AGND. For example, a 27.4 kΩ resistor sets ~1.6 MHz. External synchronization is also supported over 330–1600 kHz using the SYNC pin with appropriate RT biasing.
What is the role of the AGND and PGND pins on the TPS54617RUVR?
AGND (Pin 1) serves as the quiet analog reference for COMP, VSENSE, SS/ENA, SYNC, and VBIAS circuits. PGND (Pins 13–20, 30–34) carries high pulsed currents from the MOSFETs and inductor. They must be connected at a single point - ideally the PowerPAD - to prevent ground noise from degrading regulation accuracy or causing instability in the feedback loop.
Can the TPS54617RUVR be used with input voltages below 3 V?
No. The TPS54617RUVR has a minimum input voltage of 3 V, enforced by its UVLO circuit (start threshold = 2.95 V). Operation below 3 V is not supported and will result in shutdown. For sub-3-V inputs, consider TI's TPS6286x or TPS6290x families, which are explicitly rated for 2.0–5.5 V operation.
TPS54617RUVR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™
- Package/Case:
- 34-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 3V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 0.891V
- Voltage - Output (Max):
- 5.4V
- Current - Output:
- 6A
- Frequency - Switching:
- 350kHz, 550kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 34-VQFN (7x3.5)
TPS54617RUVR FAQ
1.How can I place an order for TPS54617RUVR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54617RUVR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54617RUVR reliable?
The price and inventory of TPS54617RUVR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54617RUVR is usually 5 days.
3.What payment methods are accepted for TPS54617RUVR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54617RUVR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54617RUVR?
TPS54617RUVR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54617RUVR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54617RUVR?
For technical support, including TPS54617RUVR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54617RUVR requirements.
6.How does Aetrix verify that TPS54617RUVR is sourced from the original manufacturer or authorized distributors?
All TPS54617RUVR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54617RUVR meets industry standards.
7.What is the process for return or replacement of TPS54617RUVR?
All TPS54617RUVR units undergo pre-shipment inspection (PSI). If there is an issue with TPS54617RUVR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54617RUVR part is unused and in its original packaging.
Return procedure for TPS54617RUVR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS54617RUVR Tags
-
TPS562201DDCR
Texas Instruments
-
MC34063ABD-TR
STMicroelectronics
-
TPS561201DDCR
Texas Instruments
-
MC33063ADR
Texas Instruments
-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments
-
AP3012KTR-G1
Diodes Incorporated
-
TLV61048DBVR
Texas Instruments
-
AZ34063UMTR-G1
Diodes Incorporated
-
TPS562200DDCR
Texas Instruments
-
AP62300TWU-7
Diodes Incorporated
-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
