Texas Instruments TPS54618RTER
- Part No.:
- TPS54618RTER
- Manufacturer:
- Texas Instruments
- Package:
- 16-WFQFN Exposed Pad
- Datasheet:
-
TPS54618RTER.pdf
- Description:
- IC REG BUCK ADJ 6A 16WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS54618RTER from Texas Instruments is a 2.95-V to 6-V, 6-A synchronous step-down DC/DC converter with integrated high- and low-side 12-mΩ MOSFETs, 0.799-V ±1% voltage reference over –40°C to +150°C, and adjustable 300-kHz to 2-MHz switching frequency via RT/CLK pin. It delivers point-of-load regulation for FPGAs and ASICs in space-constrained industrial and telecom systems.
For engineers reviewing the TPS54618RTER datasheet, TPS54618RTER pinout, TPS54618RTER application, or TPS54618RTER equivalent, key selection considerations include its WQFN-16 thermal-pad package, power-good (PWRGD) open-drain output with 93–107% VOUT window, slow-start/tracking (SS/TR) capability, and synchronization support for system-level clock alignment.
Technical Context
The TPS54618RTER implements peak current-mode control with internal slope compensation to prevent subharmonic oscillation across 0–100% duty cycle range, enabling stable operation up to 2-MHz switching. Its transconductance error amplifier (245 μA/V normal mode, 79 μA/V during soft-start) compares VSENSE against either the 0.799-V reference or SS/TR voltage.
It features an integrated boot regulator requiring only a 0.1-μF ceramic capacitor between BOOT and PH pins, supports 100% duty-cycle operation when BOOT–PH > 2.2 V, and includes frequency foldback during overcurrent events to limit inductor current. The EN pin provides programmable UVLO using external resistors and internal 1.6-μA hysteresis current source.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.95 V to 6 V - supports single-cell Li-ion, 3.3-V, and 5-V intermediate bus rails without pre-regulation. |
| Output Current | 6 A continuous - enables single-chip supply for mid-power FPGAs and DSPs without external current sharing. |
| Voltage Reference | 0.799 V ±1% over –40°C to +150°C - ensures <±12 mV output accuracy across full junction temperature range. |
| Switching Frequency | 300 kHz to 2 MHz - allows optimization of size (high-freq) vs. efficiency (low-freq) with resistor or external clock on RT/CLK. |
| Quiescent Current | 515 μA typical - minimizes no-load power loss in always-on subsystems; drops to 5.5 μA in shutdown. |
| Power-Good Window | 93% to 107% of VOUT - provides reliable system sequencing and fault detection with 2% hysteresis. |
| MOSFET RDS(on) | 12 mΩ high-side / 13 mΩ low-side (typical at 5 V VIN) - enables >90% efficiency at 5-V input, 1.8-V/4-A output. |
Pinout & Package
TPS54618RTER uses a thermally enhanced 3.00 mm × 3.00 mm, 16-pin WQFN package with exposed PowerPad for PCB ground connection and improved thermal dissipation (RθJB = 15.96°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pins 1, 2, 16) | Input power supply input | Accepts 2.95–6 V; multiple pins reduce trace resistance and improve current handling for 6-A operation. |
| PH (Pin 10) | Switch node | Connects to inductor; source of high-side MOSFET and drain of low-side MOSFET - critical for layout EMI control. |
| BOOT (Pin 13) | High-side gate drive bootstrap | Requires 0.1-μF X7R/X5R ceramic capacitor to PH; UVLO disables high-side if BOOT–PH falls below 2.1 V. |
| VSENSE (Pin 6) | Feedback sense input | Inverting input of error amplifier; sets output voltage via resistor divider; referenced to 0.799-V internal bandgap. |
| COMP (Pin 7) | Error amplifier output | Drives PWM comparator; connects to RC compensation network for loop stability across load/line conditions. |
| EN (Pin 15) | Enable / UVLO control | Pull below 1.18 V to disable; internal 1.6-μA pullup enables floating-pin default operation and programmable UVLO. |
| SS/TR (Pin 9) | Slow-start / tracking input | 2-μA internal current source charges external capacitor for controlled VOUT ramp; supports supply sequencing. |
| PWRGD (Pin 14) | Open-drain power-good output | Asserts low when VOUT is outside 93–107% window; requires external pullup; indicates valid regulation status. |
| RT/CLK (Pin 8) | Frequency setting / sync input | Resistor-to-ground sets fSW; accepts external clock (300–2000 kHz) with PLL lock time of 42 μs at 500 kHz. |
| AGND (Pin 5), GND (Pins 3, 4, 11, 12) | Analog & power ground | AGND must connect to GND near device; PowerPad (thermal pad) is GND and must be soldered with multiple vias. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated dual MOSFETs | 12-mΩ high-side + 13-mΩ low-side (typ.) enable compact 6-A design without external switches or drivers. |
| Synchronization capability | RT/CLK pin accepts external clock (300–2000 kHz) with PLL lock - eliminates beat frequencies in multi-rail systems. |
| Adjustable soft-start & tracking | SS/TR pin with 2-μA charge current enables precise output ramp control and coordinated power-up with other rails. |
| Robust fault protection | Includes frequency foldback during overcurrent, thermal shutdown (168°C), and UV/OV detection via PWRGD. |
| Wide operating temperature | –40°C to +150°C junction range - qualified for industrial, telecom, and automotive under-hood applications. |
Applications
| Point-of-Load FPGA Supply | Industrial PLC I/O Module |
|---|---|
|
Use Scenario: Powers core logic and I/O banks of mid-range FPGAs (e.g., Xilinx Artix-7, Intel Cyclone V) in programmable logic controllers. IC Role / Device Role / Timing Role: Primary synchronous buck regulator delivering tightly regulated 1.05 V, 1.2 V, or 1.8 V at up to 6 A with fast transient response. Use Value: Integrated MOSFETs and 0.799-V reference ensure ±1% output accuracy across temperature, reducing need for post-regulation LDOs. |
Use Scenario: Supplies isolated microcontroller, ADC, and digital I/O circuitry in DIN-rail mounted industrial automation modules. IC Role / Device Role / Timing Role: Main 3.3-V or 5-V DC/DC converter with PWRGD signaling to enable safe startup sequencing and watchdog reset coordination. Use Value: 150°C max junction rating and robust UVLO/thermal protection allow reliable operation in unventilated enclosures up to 85°C ambient. |
| Broadband Optical Line Card | Network Packet Processor Board |
|
Use Scenario: Provides 1.2-V core and 2.5-V I/O rails for SFP+ transceivers and forward error correction (FEC) ASICs in optical transport equipment. IC Role / Device Role / Timing Role: High-frequency (1–2 MHz) buck converter minimizing inductor size while maintaining >90% efficiency at partial load. Use Value: RT/CLK synchronization aligns switching edges across multiple rails, suppressing conducted EMI in dense line-card layouts. |
Use Scenario: Delivers 1.1-V core voltage to multi-core network processors (e.g., NXP LX2160A) in 5G baseband units and edge routers. IC Role / Device Role / Timing Role: High-current, low-noise buck regulator with SS/TR tracking to coordinate with DDR4 memory rail during cold boot. Use Value: 6-A capability eliminates parallel ICs; 2-μA SS/TR charge current enables repeatable 10–100-ms startup ramps for deterministic firmware initialization. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54418RTER | Pin-compatible 4-A version with identical pinout, package, and feature set; lower current rating and 8-mΩ MOSFETs. | Suitable for lower-power FPGAs or microcontrollers where 4-A headroom suffices; not rated for 6-A continuous loads. | Select when board reuse is critical and output current demand is ≤4 A; verify thermal margin with RθJA = 44.38°C/W. |
| MP2315DJ-LF-Z | Monolithic 6-A buck with 3.3–18-V input, fixed 500-kHz fSW, no RT/CLK sync, no SS/TR, smaller 2-mm × 2-mm QFN. | Targeted at cost-sensitive consumer/industrial apps; lacks sequencing, sync, and wide-temp qualification (–40°C to +125°C only). | Choose for simpler, lower-cost designs without clock sync or extended temperature needs; confirm PWRGD compatibility. |
Compared with TPS54618RTER, TPS54418RTER offers identical integration and layout but reduced current capacity, while MP2315DJ-LF-Z trades flexibility (no sync, no SS/TR) for smaller footprint and lower BOM cost - neither is pin-compatible beyond shared WQFN-16 outline.
Availability
TPS54618RTER is available at Aetrix Electronics and suitable for industrial automation, optical networking infrastructure, and FPGA-based embedded computing requiring stable component supply and long-term production continuity.
Supply support for TPS54618RTER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability DC/DC conversion.
The TPS54618RTER belongs to TI's SWIFT™ synchronous buck converter family, designed specifically for high-density, high-efficiency point-of-load regulation in telecom, industrial, and computing applications demanding precision, thermal robustness, and system-level timing control.
FAQ
What is the maximum recommended operating junction temperature for the TPS54618RTER?
The TPS54618RTER is rated for continuous operation up to +150°C junction temperature, with thermal shutdown activating at 168°C and 20°C hysteresis. This enables deployment in sealed industrial enclosures and telecom line cards without forced air cooling, provided PCB thermal design meets RθJB = 15.96°C/W specification using the exposed PowerPad.
How does the TPS54618RTER achieve 100% duty-cycle operation?
The TPS54618RTER achieves near-100% duty cycle by monitoring BOOT–PH voltage; when it exceeds 2.2 V, the high-side MOSFET remains on continuously. The integrated boot regulator sustains gate drive with minimal current draw, allowing extended conduction without external bootstrap diode - critical for low-dropout applications like 3.3-V-to-3.0-V conversion.
Can the TPS54618RTER synchronize to an external clock, and what are the timing requirements?
Yes, the TPS54618RTER supports external clock synchronization via the RT/CLK pin across 300–2000 kHz. It features a PLL with 42-μs lock time at 500 kHz, requires minimum 75-ns CLK pulse width, and accepts logic-high thresholds of 1.6–2.2 V. This eliminates beat frequencies in multi-rail systems and simplifies EMI filtering.
What is the function of the SS/TR pin on the TPS54618RTER, and how is it used in practice?
The SS/TR pin on the TPS54618RTER provides slow-start and voltage tracking. An external capacitor (charged by internal 2-μA current source) controls output voltage ramp time; when tied to another rail's feedback node, it enables precise power sequencing. During faults (UVLO, thermal), the pin discharges to ensure repeatable restart behavior.
Does the TPS54618RTER require an external bootstrap diode?
No, the TPS54618RTER integrates the bootstrap recharge diode, eliminating the need for an external component. Only a 0.1-μF X7R/X5R ceramic capacitor between BOOT and PH pins is required. This reduces BOM count, improves reliability, and simplifies layout - a key differentiator versus discrete controller solutions.
TPS54618RTER Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™
- Package/Case:
- 16-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.95V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 0.799V
- Voltage - Output (Max):
- 4.5V
- Current - Output:
- 6A
- Frequency - Switching:
- 200kHz ~ 2MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WQFN (3x3)
TPS54618RTER FAQ
1.How can I place an order for TPS54618RTER through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54618RTER on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54618RTER reliable?
The price and inventory of TPS54618RTER are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54618RTER is usually 5 days.
3.What payment methods are accepted for TPS54618RTER?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54618RTER transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54618RTER?
TPS54618RTER orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54618RTER order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54618RTER?
For technical support, including TPS54618RTER datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54618RTER requirements.
6.How does Aetrix verify that TPS54618RTER is sourced from the original manufacturer or authorized distributors?
All TPS54618RTER products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54618RTER meets industry standards.
7.What is the process for return or replacement of TPS54618RTER?
All TPS54618RTER units undergo pre-shipment inspection (PSI). If there is an issue with TPS54618RTER, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54618RTER part is unused and in its original packaging.
Return procedure for TPS54618RTER:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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