Texas Instruments TPS54620RHLR

Overview

TPS54620 from Texas Instruments is a 4.5-V to 17-V input, 6-A synchronous step-down DC/DC converter in a thermally enhanced 3.50 mm × 3.50 mm VQFN-14 package. It integrates 26 mΩ high-side and 19 mΩ low-side MOSFETs, supports 200 kHz–1.6 MHz adjustable switching frequency via RT/CLK pin, delivers 0.8 V ±1% reference accuracy over temperature, and features monotonic start-up into prebiased outputs for use in high-density point-of-load power rails.

For engineers reviewing the TPS54620 datasheet, TPS54620 pinout, TPS54620 application, or TPS54620 equivalent, key selection considerations include its split-rail PVIN/VIN architecture (1.6 V–17 V / 4.5 V–17 V), integrated BOOT-PH UVLO (2.1 V), 2-µA shutdown quiescent current, and open-drain PWRGD with 91–109% VREF fault window for reliable system power sequencing.

Technical Context

The TPS54620 employs constant-frequency peak current-mode control with internal slope compensation to prevent subharmonic oscillation across full duty cycle range. Its transconductance error amplifier (1300 µA/V) drives COMP to regulate VSENSE against either the 0.8-V internal reference or SS/TR voltage, enabling tracking and sequencing.

It implements dual overload protection: high-side current limit (8–11 A), low-side sourcing limit (7–10 A), and low-side sinking limit (2.3 A), plus thermal shutdown at 160–175°C with 10°C hysteresis. The BOOT-PH UVLO ensures boot capacitor recharge before high-side turn-on, supporting 100% duty-cycle operation when BOOT-PH > 2.1 V.

Key Specifications

Pinout & Package

TPS54620 is housed in a 3.50 mm × 3.50 mm, 14-pin VQFN package (RHL) with an exposed thermal pad (Pin 15) requiring solder connection to PCB ground plane for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-down converter applications.

Compared with TPS54560RTER and MP2451DT-LF-Z, the TPS54620 uniquely combines 6-A capability with split-rail flexibility, monotonic prebias start-up, and comprehensive fault reporting via PWRGD-making it optimal for space-constrained, multi-rail embedded systems requiring robust sequencing and thermal resilience.

Availability

TPS54620 is available at Aetrix Electronics and suitable for high-density distributed power systems, high-performance point-of-load regulation, and broadband communications infrastructure requiring stable component supply and long-term production continuity.

Supply support for TPS54620 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and power management technologies with broad industrial, automotive, and communications reach.

The TPS54620 belongs to TI's SWIFT™ synchronous buck converter product line, designed specifically for high-efficiency, high-current, space-constrained point-of-load applications demanding integrated power stages and advanced sequencing capabilities.

FAQ

What is the minimum input voltage required for TPS54620 to operate normally?

The TPS54620 requires VIN ≥ 4.5 V to power its internal control circuitry, while PVIN can operate as low as 1.6 V for the power stage. If both pins are tied together, the minimum valid input is 4.5 V. Below this, the device enters undervoltage lockout (UVLO) and ceases switching. The internal VIN UVLO threshold is 4.0 V (rising) with 150 mV hysteresis, ensuring clean startup and shutdown behavior in the TPS54620.

How does the TPS54620 support power supply sequencing in multi-rail systems?

The TPS54620 supports sequencing via three dedicated features: the SS/TR pin controls output voltage ramp rate or tracks another supply, the EN pin enables/disable timing control with configurable UVLO, and the open-drain PWRGD pin signals "good" output status (94–106% VREF) to enable downstream regulators. These allow precise coordination of core, I/O, and auxiliary rails without external sequencers - a key capability built into the TPS54620 architecture.

Can the TPS54620 safely start up into a precharged output, and how is this achieved?

Yes, the TPS54620 guarantees monotonic start-up into prebiased outputs. During startup, the low-side MOSFET is disabled from sinking current until the SS/TR pin voltage exceeds 1.4 V - preventing reverse current flow that could collapse the precharged rail. This behavior is hard-coded in the TPS54620's internal logic and requires no external components, making it ideal for hot-swap and redundant power applications where the TPS54620 is added to an already active system.

What is the role of the BOOT-PH UVLO circuit in the TPS54620, and what happens if it triggers?

The BOOT-PH UVLO monitors the voltage across the bootstrap capacitor (between BOOT and PH pins). If BOOT-PH falls below 2.1 V (typical), the TPS54620 disables the high-side MOSFET and forces PH low to recharge the capacitor. This prevents shoot-through and ensures sufficient gate drive for reliable high-side turn-on. Triggering indicates insufficient boot capacitance, excessive switching frequency, or layout parasitics - all resolvable by optimizing Cboot value and placement in the TPS54620 design.

Does the TPS54620 support synchronization to an external clock, and how is it configured?

Yes, the TPS54620 supports external clock synchronization via the RT/CLK pin. When an external clock signal with amplitude > 2 V (high) and < 0.8 V (low) is applied, the internal PLL locks to its falling edge, overriding the RT resistor setting. This enables precise phase alignment across multiple TPS54620 converters in dense power systems - critical for EMI reduction and current sharing. No additional components are needed beyond the clock source; the TPS54620 automatically detects and transitions to CLK mode.