Texas Instruments TPS54622RHLR

Overview

TPS54622RHLR from Texas Instruments is a 4.5-V to 17-V input, 6-A synchronous step-down DC/DC converter in a thermally enhanced 3.5-mm × 3.5-mm VQFN-14 package with exposed thermal pad. It integrates 26-mΩ high-side and 19-mΩ low-side N-channel MOSFETs, features 200-kHz to 1.6-MHz adjustable switching frequency, 0.6-V ±1% reference, hiccup current limiting, and power-good monitoring - enabling compact, high-efficiency point-of-load regulation for telecom and networking infrastructure.

For engineers reviewing the TPS54622RHLR datasheet, TPS54622RHLR pinout, TPS54622RHLR application, or TPS54622RHLR equivalent, key selection considerations include its split-rail PVIN/VIN architecture (1.6 V–17 V / 4.5 V–17 V), monotonic prebiased start-up capability, RT/CLK synchronization support, BOOT-PH UVLO threshold (2.1 V typical), and thermal shutdown with hiccup recovery (16384-cycle delay).

Technical Context

The TPS54622RHLR employs peak-current-mode control with internal slope compensation to prevent subharmonic oscillation across 0–100% duty cycle. Its dual-input architecture separates control logic supply (VIN) from power stage supply (PVIN), enabling operation down to 1.6 V on PVIN while maintaining full functionality at VIN ≥ 4.5 V.

It implements bidirectional low-side current limiting (6.5–15 A sourcing, 2–4 A sinking) and high-side overcurrent protection (8–14 A), coordinated with thermal shutdown (160–175°C trip) and hiccup recovery (512-cycle wait, 16384-cycle restart). The SS/TR pin controls ramp rate and enables tracking/sequencing by overriding the 0.6-V reference.

Key Specifications

Pinout & Package

TPS54622RHLR uses a 14-pin VQFN package (3.5 mm × 3.5 mm) with an exposed thermal pad (Pin 15) that must be soldered to PCB ground for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous step-down converter applications.

Compared with TPS54622RHLR, TPS54620RHLR offers lower cost but sacrifices hiccup protection and thermal efficiency, while MP2315DJ-LF-Z provides wider input range but lacks critical features for telecom and high-reliability sequencing - making TPS54622RHLR the optimal choice for demanding POL applications requiring robust fault handling and precise coordination.

Availability

TPS54622RHLR is available at Aetrix Electronics and suitable for high-density distributed power systems, high-performance point-of-load regulation, and broadband communications infrastructure requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for TPS54622RHLR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and power management ICs with broad industrial, automotive, and communications reach.

The TPS54622RHLR belongs to TI's SWIFT™ synchronous buck converter family, designed specifically for high-efficiency, high-current point-of-load regulation in space-constrained telecom, networking, and optical infrastructure equipment.

FAQ

What is the minimum input voltage supported by the TPS54622RHLR on its PVIN pin?

The TPS54622RHLR supports a minimum input voltage of 1.6 V on the PVIN pin, enabling operation from low-voltage intermediate buses such as 1.8-V or 2.5-V rails. This split-rail architecture decouples power stage supply from control circuitry (VIN), allowing full functionality even when PVIN is as low as 1.6 V - a key advantage over conventional single-input buck converters. The TPS54622RHLR maintains regulation, current limiting, and protection features across this extended PVIN range.

How does the TPS54622RHLR achieve monotonic start-up into a prebiased output?

The TPS54622RHLR achieves monotonic start-up into a prebiased output by disabling low-side MOSFET sinking current until the SS/TR pin voltage exceeds 1.4 V. During initial power-up, the internal 0.6-V reference is overridden by the rising SS/TR voltage, preventing the error amplifier from commanding negative duty cycle. This ensures the output voltage ramps cleanly from zero without discharging the precharged rail. The TPS54622RHLR implements this behavior natively - no external components are required to guarantee monotonicity.

What is the purpose of the BOOT-PH UVLO threshold in the TPS54622RHLR, and what is its typical value?

The BOOT-PH UVLO threshold in the TPS54622RHLR monitors the bootstrap capacitor voltage to ensure sufficient gate drive for the high-side MOSFET. If BOOT-PH falls below the threshold, the high-side switch is disabled to prevent shoot-through and maintain control. Its typical value is 2.1 V, with a guaranteed minimum of 2.1 V and maximum of 3.0 V across temperature and process. This feature allows the TPS54622RHLR to operate reliably at 100% duty cycle as long as BOOT-PH remains above this threshold - critical for low-dropout applications.

Can the TPS54622RHLR synchronize its switching frequency to an external clock, and how is this configured?

Yes, the TPS54622RHLR can synchronize its switching frequency to an external clock via the RT/CLK pin. When an external clock signal with amplitude >2 V (high) and <0.8 V (low) is applied, the internal PLL locks to its falling edge - automatically entering CLK mode and disabling the internal oscillator. No external components are needed beyond the clock source. In RT mode, a resistor from RT/CLK to GND sets frequency from 200 kHz to 1.6 MHz. The TPS54622RHLR detects mode automatically based on signal level and edge timing.

What thermal metrics define the TPS54622RHLR's ability to dissipate heat, and how should the exposed thermal pad be handled?

The TPS54622RHLR's thermal performance is defined by R_θJCbot = 1.8°C/W (junction-to-case bottom), R_θJB = 11.4°C/W (junction-to-board), and R_θJA = 40.1°C/W (junction-to-ambient, measured per JEDEC JESD51-7). The exposed thermal pad (Pin 15) must be soldered to a dedicated PCB copper area connected to ground - at minimum, four 0.010-inch thermal vias under the pad are recommended. Failure to solder the pad degrades thermal performance significantly and risks thermal shutdown under load.