Texas Instruments TPS54625PWP
- Part No.:
- TPS54625PWP
- Manufacturer:
- Texas Instruments
- Package:
- 14-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS54625PWP.pdf
- Description:
- IC REG BUCK ADJ 6.5A 14HTSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS54625PWP from Texas Instruments is a 6.5-A synchronous step-down DC/DC converter with integrated high-side (36 mΩ) and low-side (28 mΩ) N-channel MOSFETs, D-CAP2™ adaptive on-time control, 650-kHz pseudo-fixed switching frequency, and 0.76–5.5-V programmable output voltage. It delivers fast transient response in digital TV power supplies and networking terminal applications.
For engineers reviewing the TPS54625PWP datasheet, TPS54625PWP pinout, TPS54625PWP application, or TPS54625PWP equivalent, key selection criteria include its HTSSOP-14 PowerPAD™ thermal package, pre-biased soft-start capability, cycle-by-cycle overcurrent protection, and compatibility with ceramic output capacitors for low ripple.
Technical Context
The TPS54625PWP implements D-CAP2™ mode control-combining adaptive on-time PWM with internal compensation-to achieve stable operation without external loop compensation components, even with ultra-low-ESR ceramic output capacitors. Its control loop monitors VFB against a 765-mV reference and uses an internal ramp to emulate ripple for regulation.
It operates in Forced Continuous Conduction Mode (FCCM) at light load to minimize output voltage ripple, supports adjustable soft start via external capacitor on SS pin, and integrates power-good monitoring with 15% UV/OV thresholds and 1.7× soft-start enable delay. Thermal shutdown activates at 165°C with 35°C hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 18 V - supports wide-input industrial and consumer power rails including 5 V, 12 V, and 15 V bus systems. |
| Output Current | 6.5 A continuous - sufficient for core logic rails in STB, Blu-ray players, and network terminals. |
| Switching Frequency | 650 kHz nominal - enables compact magnetics and balances efficiency vs. EMI performance. |
| Feedback Reference | 765 mV ±2 mV (25°C), ±8 mV (–40°C to 85°C) - ensures tight output voltage accuracy across temperature. |
| High-Side RDS(on) | 36 mΩ - reduces conduction loss at high duty cycles, improving efficiency in 3.3 V/5 V output configurations. |
| Low-Side RDS(on) | 28 mΩ - minimizes synchronous rectification loss, critical for high-current, low-VOUT operation. |
| Shutdown Current | ≤10 μA - enables ultra-low quiescent power in standby or battery-backed systems. |
| Thermal Protection | 165°C trip with 35°C hysteresis - prevents permanent damage during overload or poor heatsinking. |
Pinout & Package
TPS54625PWP is housed in a thermally enhanced 14-pin HTSSOP (PowerPAD™) package with exposed thermal pad soldered to PGND for optimal junction-to-board heat transfer (θJB = 24.2°C/W). The package supports –40°C to 85°C ambient operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VO (Pin 1) | Output voltage node | Connects to LC filter output; provides internal discharge path to GND when EN = low. |
| VFB (Pin 2) | Feedback input | Monitors output via resistor divider; 765-mV reference sets regulated VOUT. |
| VREG5 (Pin 3) | Internal 5.5-V LDO output | Powers internal circuitry; requires 1-μF ceramic cap to PGND; inactive when EN = low. |
| SS (Pin 4) | Soft-start control | External capacitor sets ramp time; supports pre-biased startup by limiting initial low-side FET conduction. |
| GND (Pin 5) | Signal ground | Reference for analog circuits; must be tied to PGND near IC for noise immunity. |
| PG (Pin 6) | Open-drain power-good | Asserts high after 1.7× soft-start time when VFB is within ±10% of target; requires 25–150-kΩ pull-up to VREG5. |
| EN (Pin 7) | Enable input | Active-high logic; internal 200–800-kΩ pull-down; threshold 0.6 V (low), 1.6 V (high). |
| PGND1, PGND2 (Pins 8,9) | Power ground returns | Low-side MOSFET source connections and current-sense inputs; must be solidly connected to thermal pad. |
| SW1, SW2 (Pins 10,11) | Switch nodes | Connect to inductor; carry high di/dt; require short, low-inductance PCB traces. |
| VBST (Pin 12) | Bootstrap supply | Drives high-side gate; requires 0.1-μF ceramic cap to SW1/SW2; internally diode-clamped to VREG5. |
| VIN1, VIN2 (Pins 13,14) | Main input power | Connect to bulk input capacitor; dual pins reduce IR drop and improve thermal distribution. |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP2™ adaptive on-time control | Enables stable regulation with zero external compensation components and supports ceramic, POSCAP, and SP-CAP output capacitors. |
| Pre-biased soft start | Prevents reverse current flow during startup into pre-charged outputs by incrementally enabling low-side FET conduction. |
| Integrated 5.5-V VREG5 LDO | Eliminates need for external bias supply; powers internal logic and VBST bootstrap circuit; shuts down with EN. |
| Cycle-by-cycle overcurrent protection | Detects valley current during low-side conduction; latches off both FETs if sustained >7.2 A (typical) limit is exceeded. |
| Output discharge function | Activates internal 100-Ω MOSFET between VO and GND during shutdown or fault, safely discharging output capacitance. |
| Thermal shutdown with hysteresis | Non-latching 165°C cutoff with 35°C recovery margin ensures safe restart after cooling without system reset. |
Applications
| Digital TV Power Supply | High Definition Blu-ray Disc™ Player |
|---|---|
Use Scenario: Supplies 1.05 V/6.5 A core voltage to SoC and memory subsystems under dynamic video decoding loads. IC Role / Device Role / Timing Role: Primary buck regulator delivering tightly regulated, low-noise core rail with sub-100-mV load transient deviation. Use Value: D-CAP2™ control achieves <100-μs recovery from 0–6.5-A load steps, minimizing required output capacitance and board area. |
Use Scenario: Powers HDMI controller, video DAC, and flash memory interface requiring clean 3.3 V at up to 4 A. IC Role / Device Role / Timing Role: Secondary buck stage converting 12 V input to 3.3 V with FCCM mode ensuring low ripple during idle playback. Use Value: 28-mΩ low-side RDS(on) and ceramic-cap-compatible design reduce RMS losses and eliminate electrolytic capacitor aging concerns. |
| Networking Home Terminal | Digital Set Top Box (STB) |
Use Scenario: Generates 1.2 V/5 A CPU core rail in cable modem or gateway devices with bursty data traffic patterns. IC Role / Device Role / Timing Role: High-efficiency synchronous buck managing rapid load transients induced by packet processing bursts. Use Value: 36-mΩ high-side RDS(on) and 650-kHz switching minimize conduction + switching losses, sustaining >92% peak efficiency at 12 VIN/1.2 VOUT. |
Use Scenario: Delivers 5 V/3 A for USB peripherals, tuners, and front-panel displays in multi-tuner STBs. IC Role / Device Role / Timing Role: Main 5-V rail generator with power-good signaling to MCU for safe boot sequencing. Use Value: Integrated PG output with 15% OV/UV thresholds and 1.7× soft-start delay ensures reliable system initialization before firmware execution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54620RGYR | Same D-CAP2™ architecture but 6-A rating, 4.5–17-V input, 16-pin QFN with wettable flanks; lacks VREG5 LDO. | Requires external 5-V bias for gate drivers; better suited for space-constrained layouts needing thermal performance above HTSSOP. | Select when PCB real estate is limited and thermal vias are feasible; avoid if VREG5 simplification is critical. |
| MP2315GJ-Z | 6-A monolithic buck with 4.5–28-V input, 340-kHz fixed frequency, no VREG5, no pre-biased soft start, 100-mA IQ in shutdown. | Higher input range suits 24-V industrial systems; less suitable for consumer-grade pre-biased startup requirements. | Choose for wider VIN or cost-sensitive designs where D-CAP2™ speed is secondary to BOM count reduction. |
Compared with TPS54625PWP, TPS54620RGYR offers superior thermal metrics but removes integrated biasing, while MP2315GJ-Z trades transient performance and startup flexibility for broader input range and lower unit cost-making TPS54625PWP optimal for consumer electronics demanding fast load response and seamless pre-bias handling.
Availability
TPS54625PWP is available at Aetrix Electronics and suitable for digital TV power supplies, HD Blu-ray player designs, and networking home terminal applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for TPS54625PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-performance DC/DC conversion.
The TPS54625 belongs to TI's D-CAP2™ synchronous buck converter product line, engineered for consumer and computing applications demanding fast transient response, minimal external components, and robust protection in compact form factors.
FAQ
What is the maximum output current supported by the TPS54625PWP?
The TPS54625PWP is rated for continuous 6.5-A output current under recommended operating conditions (TA ≤ 85°C, proper PCB thermal design). Its cycle-by-cycle overcurrent protection triggers at 7.2–9.5 A (typ–max), allowing brief peak loads while maintaining reliability. Derating applies above 85°C ambient or with insufficient copper area on the PowerPAD™ thermal pad.
Does the TPS54625PWP support pre-biased output startup?
Yes, the TPS54625PWP includes proprietary pre-biased soft-start circuitry that prevents reverse current flow during startup into a pre-charged output. It does so by gradually increasing low-side FET conduction time until reaching normal duty-cycle operation-ensuring smooth, safe ramp-up without damaging downstream circuitry or causing bus contention.
What package type and thermal characteristics define the TPS54625PWP?
The TPS54625PWP uses a 14-pin HTSSOP package with PowerPAD™-an exposed thermal pad soldered directly to PGND. Its junction-to-board thermal resistance (θJB) is 24.2°C/W, and junction-to-ambient (θJA) is 40.5°C/W with standard 2-layer board layout. Full thermal performance requires ≥4 thermal vias under the pad connected to inner ground planes.
How does the D-CAP2™ control mode in the TPS54625PWP differ from traditional voltage-mode or current-mode control?
D-CAP2™ is an adaptive on-time control scheme that eliminates external compensation components by embedding internal ramp generation and pseudo-fixed-frequency behavior. Unlike voltage-mode (requires Type II/III compensation) or current-mode (needs slope compensation), D-CAP2™ achieves stability with ceramic capacitors alone and delivers faster transient response-typically <100 μs for full-load steps-due to direct feedback of output voltage ripple emulation.
Can the TPS54625PWP operate with only ceramic output capacitors?
Yes, the TPS54625PWP is explicitly designed for ceramic output capacitors. Its D-CAP2™ control architecture includes internal circuitry that adapts to ultra-low-ESR ceramics (down to ~2 mΩ), eliminating the need for high-ESR tantalum or polymer capacitors. Typical designs use 22–68 μF total ceramic capacitance, often split across multiple 1206 or 0805 case sizes for optimal high-frequency filtering.
TPS54625PWP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP2™
- Package/Case:
- 14-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 18V
- Voltage - Output (Min/Fixed):
- 0.765V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 6.5A
- Frequency - Switching:
- 650kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-HTSSOP
TPS54625PWP FAQ
1.How can I place an order for TPS54625PWP through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54625PWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54625PWP reliable?
The price and inventory of TPS54625PWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54625PWP is usually 5 days.
3.What payment methods are accepted for TPS54625PWP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54625PWP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54625PWP?
TPS54625PWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54625PWP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54625PWP?
For technical support, including TPS54625PWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54625PWP requirements.
6.How does Aetrix verify that TPS54625PWP is sourced from the original manufacturer or authorized distributors?
All TPS54625PWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54625PWP meets industry standards.
7.What is the process for return or replacement of TPS54625PWP?
All TPS54625PWP units undergo pre-shipment inspection (PSI). If there is an issue with TPS54625PWP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54625PWP part is unused and in its original packaging.
Return procedure for TPS54625PWP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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