Texas Instruments TPS54672PWPRG4
- Part No.:
- TPS54672PWPRG4
- Manufacturer:
- Texas Instruments
- Package:
- 28-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS54672PWPRG4.pdf
- Description:
- IC REG BUCK 6A 28HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,353
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Product details
Overview
TPS54672PWPRG4 from Texas Instruments is a synchronous PWM bus termination regulator IC designed for DDR memory and GTL/STL active termination. It delivers ±6 A continuous output current with 30-mΩ high- and low-side MOSFETs, supports 3 V to 6 V input, tracks external reference voltages from 0.2 V to 1.75 V, and operates at fixed 350 kHz or adjustable 280–700 kHz switching frequency.
For engineers reviewing the TPS54672PWPRG4 datasheet, TPS54672PWPRG4 pinout, TPS54672PWPRG4 application, or TPS54672PWPRG4 equivalent, key selection considerations include its dual-source/sink capability, thermal shutdown at 150°C, ±1.5% cumulative regulation accuracy over load, integrated VBIAS regulator (2.8 V typical), and PowerPAD-enabled thermal performance in the 28-pin HTSSOP package.
Technical Context
The TPS54672PWPRG4 implements a synchronous buck topology with adaptive dead-time control to prevent shoot-through, using internal high- and low-side N-MOSFETs (rDS(on) = 26–47 mΩ at 6 VIN). Its error amplifier features 5 MHz unity-gain bandwidth, 1.4 V/µs slew rate, and rail-to-rail input range - enabling precise tracking of externally applied REFIN signals across wide load and line conditions.
Control architecture integrates under-voltage lockout (UVLO start at 2.95 V), slow-start (0.25 V/ms), cycle-by-cycle current limiting (10–12 A trip point), and open-drain STATUS signaling for system-level power sequencing. The RT pin allows resistor-programmable oscillator frequency, while PH pins (6–14) serve as the high-current phase node tied directly to the output inductor.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.0 V to 6.0 V - supports DDR VDDQ rails and intermediate bus architectures without pre-regulation. |
| Continuous Output Current | ±6 A - enables bidirectional sourcing/sinking for DDR VTT termination with no external FETs required. |
| Switching Frequency | Fixed 350 kHz or 280–700 kHz adjustable - balances efficiency, size, and EMI in dense PCB layouts. |
| Cumulative Regulation Accuracy | ±1.5% over −6 A to +6 A load - ensures stable DDR termination voltage under dynamic memory access. |
| Thermal Shutdown Threshold | 150°C with 10°C hysteresis - protects against sustained overload or poor heatsinking in compact systems. |
| VBIAS Output | 2.8 V typical at 100 µA - powers internal circuitry and can serve as a clean bias reference for external circuits. |
| UVLO Start/Stop Threshold | 2.95 V / 2.80 V - prevents erratic startup during brown-out and ensures graceful shutdown. |
Pinout & Package
The TPS54672PWPRG4 is housed in a thermally enhanced 28-pin HTSSOP (PWP) PowerPAD package measuring 6.4 mm × 9.7 mm, with an exposed thermal pad soldered to AGND for efficient heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND (Pin 1) | Analog ground reference | Return path for compensation network, VBIAS capacitor, and RT resistor; must connect to PowerPAD for optimal noise immunity. |
| VSENSE (Pin 2) | Error amplifier inverting input | Monitors output voltage via resistive divider; enables precision feedback for tracking applications. |
| COMP (Pin 3) | Error amplifier output | Drives external Type 2/3 compensation network to stabilize loop response across load transients. |
| STATUS (Pin 4) | Open-drain fault indicator | Asserts low during UVLO, thermal shutdown, or VBIAS undervoltage - used for system power sequencing. |
| BOOT (Pin 5) | Bootstrap gate drive supply | Connects to PH through 0.022–0.1 µF ceramic capacitor to generate floating voltage for high-side FET driver. |
| PH (Pins 6–14) | Phase node | High-current switching junction between internal MOSFETs; connects directly to output inductor with minimal trace area. |
| RT (Pin 28) | Oscillator frequency set | Resistor to AGND sets frequency from 280–700 kHz; floating defaults to 350 kHz. |
| ENA (Pin 27) | Enable control input | Logic-high ≥1.4 V enables operation; logic-low ≤0.82 V disables with 1.4 mA shutdown current. |
| REFIN (Pin 26) | External reference input | High-impedance input (60–250 nA bias) accepting 0–1.8 V reference for tracking DDR VDDQ or other sources. |
| VBIAS (Pin 25) | Internal bias regulator output | Provides 2.7–2.9 V regulated supply; requires 0.1–1.0 µF ceramic bypass to AGND for stability. |
| VIN (Pins 20–24) | Main power input | Accepts 3–6 V input; multiple pins reduce IR drop and improve current sharing into internal regulators and FETs. |
| PGND (Pins 15–19) | Power ground return | High-current return for low-side FET and input/output capacitors; separate from AGND to minimize noise coupling. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated high- and low-side MOSFETs | 30-mΩ rDS(on) at 6 VIN enables >90% efficiency at 6 A without external switches or drivers. |
| Active bus termination capability | Sinks and sources up to 6 A continuously - meets JEDEC DDR1/DDR2 VTT requirements with single-chip solution. |
| Tracking reference input (REFIN) | Accepts 0.2–1.75 V external reference with ±1.5 mV offset - supports dynamic VDDQ tracking in memory subsystems. |
| Thermally optimized PowerPAD package | 28-pin HTSSOP with exposed thermal pad reduces θJA to 18.2°C/W (with solder), enabling 6 A operation without heatsink. |
| Robust protection suite | Includes cycle-by-cycle current limit (10–12 A), thermal shutdown (150°C), UVLO, and soft-start - eliminates need for external supervision. |
Applications
| DDR Memory Termination | Active GTL/STL Bus Termination |
|---|---|
|
Use Scenario: Providing matched VTT termination voltage for DDR SDRAM modules operating at 1.25 V, 1.5 V, or 1.8 V with fast load transients during read/write bursts. IC Role / Device Role / Timing Role: Bidirectional synchronous buck regulator acting as active termination sink/source, tightly tracking VDDQ with <10 µs transient response. Use Value: Eliminates discrete termination resistors and external FETs, reducing BOM count by ≥7 components while maintaining ±1.5% regulation under ±6 A step loads. |
Use Scenario: Terminating high-speed GTL+ or STL buses in telecom backplanes where impedance matching must adapt to varying signal swing and temperature drift. IC Role / Device Role / Timing Role: Precision tracking regulator sourcing/sinking current to maintain bus voltage within ±25 mV of reference during signal transitions. Use Value: Achieves <50 mV peak-to-peak ripple under 2 A/div load steps, enabling reliable 100+ MHz bus operation without external compensation tuning. |
| DAC-Controlled High-Current Stage | Precision Point-of-Load Supply |
|
Use Scenario: Converting DAC output (e.g., 0–1.25 V) into programmable 0–1.25 V, ±6 A supply for analog test equipment calibration stages. IC Role / Device Role / Timing Role: Reference-tracking regulator interpreting DAC voltage as REFIN, delivering fast-settling, low-noise current to DUT loads. Use Value: Leverages 1.4 V/µs COMP slew rate and 5 MHz error amp bandwidth to achieve <100 µs settling time from 0 to full-scale output. |
Use Scenario: Delivering tightly regulated 1.25 V at up to 6 A to FPGA I/O banks or ASIC core logic where voltage margin is ≤3%. IC Role / Device Role / Timing Role: High-accuracy buck converter with ±1.5% regulation and 0.35 V/ms max ramp - ensuring safe power-up sequencing. Use Value: Maintains output within specification across −40°C to 85°C ambient, with thermal shutdown preventing damage during airflow loss or enclosure overheating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar active bus termination regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54673PWPR | Disables sink current during startup to prevent negative VTT overshoot; identical pinout and specs otherwise. | Better suited for systems requiring monotonic VTT ramp-up without undershoot on power-on reset. | Select TPS54673PWPR when DDR initialization mandates strict non-negative VTT behavior during boot. |
| TPS54972PWPR | Higher 9-A continuous output rating; same 28-pin PWP package but with 18-mΩ MOSFETs and extended 3–18 V input range. | Targets DDR3/DDR4 VTT and higher-current GTL applications where >6 A headroom is needed. | Choose TPS54972PWPR for future-proofing or designs requiring >6 A sink capability with minimal layout change. |
Compared with TPS54672PWPRG4, TPS54673PWPR adds startup sink disable for safer DDR initialization, while TPS54972PWPR extends current capacity and input range - both retain identical footprint and tracking functionality but address distinct reliability and scalability needs.
Availability
TPS54672PWPRG4 is available at Aetrix Electronics and suitable for DDR memory termination, active GTL/STL bus termination, and precision point-of-load power supplies requiring stable component supply, consistent thermal performance, and long-term industrial lifecycle support.
Supply support for TPS54672PWPRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-efficiency DC/DC conversion.
The TPS54672PWPRG4 belongs to TI's SWIFT™ family of synchronous buck regulators, engineered specifically for high-current, low-voltage active termination in memory and high-speed digital interfaces.
FAQ
What is the maximum continuous output current capability of the TPS54672PWPRG4?
The TPS54672PWPRG4 supports ±6 A continuous output current in both sourcing and sinking directions. This bidirectional capability is essential for DDR memory VTT termination, where current flows into or out of the bus depending on data state. The device achieves this using integrated 30-mΩ high- and low-side N-MOSFETs, eliminating external switches while maintaining >90% efficiency at full load.
Does the TPS54672PWPRG4 require external MOSFETs for DDR termination?
No, the TPS54672PWPRG4 does not require external MOSFETs for DDR termination. It integrates matched high- and low-side N-channel MOSFETs with 26–47 mΩ rDS(on) into a single 28-pin HTSSOP PowerPAD package. This monolithic design replaces discrete FETs, gate drivers, and associated passives - reducing board area, component count, and layout complexity while ensuring matched timing and thermal behavior.
How does the TPS54672PWPRG4 track an external reference voltage like DDR VDDQ?
The TPS54672PWPRG4 tracks external references via its REFIN pin (Pin 26), which accepts 0.2–1.75 V with high impedance (60–250 nA bias current) and ±1.5 mV offset. When VDDQ varies dynamically, REFIN follows it, and the internal error amplifier adjusts duty cycle to maintain VTT = VDDQ/2 or other ratio-defined termination voltage - enabling JEDEC-compliant DDR1/DDR2 operation without additional op-amps or DACs.
What thermal management features does the TPS54672PWPRG4 include?
The TPS54672PWPRG4 incorporates thermal shutdown at 150°C with 10°C hysteresis, plus a thermally enhanced 28-pin HTSSOP PowerPAD package. With proper PCB layout - including soldered thermal pad, ≥8 vias under the pad, and connection to ≥3″×3″ 1-oz copper plane - it achieves θJA = 18.2°C/W, enabling 6 A operation at 85°C ambient without external heatsink. Thermal performance is validated per TI SLMA002 guidelines.
Can the TPS54672PWPRG4 be used in applications requiring adjustable switching frequency?
Yes, the TPS54672PWPRG4 supports adjustable switching frequency from 280 kHz to 700 kHz via an external resistor connected between RT (Pin 28) and AGND. Leaving RT floating selects the default 350 kHz internal oscillator. The frequency is calculated as ≈500 kHz × (100 kΩ / R), allowing designers to optimize for efficiency (lower f), size (higher f), or EMI compliance - all without changing the TPS54672PWPRG4 part number or layout.
TPS54672PWPRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™
- Package/Case:
- 28-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- -
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 3V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- -
- Voltage - Output (Max):
- -
- Current - Output:
- 6A
- Frequency - Switching:
- 350kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-HTSSOP
TPS54672PWPRG4 FAQ
1.How can I place an order for TPS54672PWPRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54672PWPRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54672PWPRG4 reliable?
The price and inventory of TPS54672PWPRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54672PWPRG4 is usually 5 days.
3.What payment methods are accepted for TPS54672PWPRG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54672PWPRG4 transactions.
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4.How is shipping managed for TPS54672PWPRG4?
TPS54672PWPRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54672PWPRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54672PWPRG4?
For technical support, including TPS54672PWPRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54672PWPRG4 requirements.
6.How does Aetrix verify that TPS54672PWPRG4 is sourced from the original manufacturer or authorized distributors?
All TPS54672PWPRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54672PWPRG4 meets industry standards.
7.What is the process for return or replacement of TPS54672PWPRG4?
All TPS54672PWPRG4 units undergo pre-shipment inspection (PSI). If there is an issue with TPS54672PWPRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54672PWPRG4 part is unused and in its original packaging.
Return procedure for TPS54672PWPRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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