Texas Instruments TPS54673PWPR

Overview

TPS54673PWPR from Texas Instruments is a 3-V to 6-V input, 6-A continuous synchronous buck PWM converter in a thermally enhanced 28-pin HTSSOP (PWP) PowerPAD™ package. It delivers adjustable 0.9-V to 3.3-V output with ±1.0% reference accuracy, features dual 30-mΩ MOSFET switches, and supports fixed 350/550 kHz or adjustable 280–700 kHz switching frequency for point-of-load regulation in FPGA power supplies.

For engineers reviewing the TPS54673PWPR datasheet, TPS54673PWPR pinout, TPS54673PWPR application, or TPS54673PWPR equivalent, key selection criteria include its disabled current sinking during startup, integrated slow-start with 3.35-ms internal timing, thermal shutdown at 150°C, UVLO with 3.0-V turn-on threshold, and compatibility with precharged output rails in high-density DSP/FPGA systems.

Technical Context

The TPS54673PWPR implements a voltage-mode synchronous buck architecture with an integrated high-performance error amplifier (110 dB open-loop gain, 5 MHz unity-gain bandwidth), adaptive dead-time control, and leading-edge blanking (100 ns) for current-sense reliability. Its oscillator supports both internal fixed-frequency modes (350/550 kHz) and external resistor-programmable operation (280–700 kHz) via the RT pin, with synchronization capability up to 700 kHz.

Startup behavior is defined by three interlocked protections: under-voltage lockout (UVLO start at 2.95 V, 0.16-V hysteresis), DSDS (Disabled Sinking During Start-up) that blocks low-side FET conduction until maximum duty cycle is reached, and slow-start via SS/ENA pin with 3.35-ms internal ramp and optional external capacitor extension.

Key Specifications

Pinout & Package

The TPS54673PWPR is housed in a 28-pin HTSSOP (PWP) package measuring 6.4 mm × 9.7 mm, featuring an exposed thermal pad (PowerPAD™) on the underside for direct PCB thermal coupling. The package requires soldering the PowerPAD to a dedicated analog ground plane with ≥12 thermal vias for rated 6-A operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck regulator applications.

Compared with TPS54673PWPR, TPS54678RTVR offers higher current capacity and wider frequency range but omits DSDS-critical for precharge-safe FPGA supplies-while LM27402SQX/NOPB provides design flexibility at the cost of increased BOM count and layout complexity.

Availability

TPS54673PWPR is available at Aetrix Electronics and suitable for point-of-load FPGA supplies, DSP processor rails, broadband optical infrastructure, and PowerPC microprocessor applications requiring stable component supply across industrial temperature ranges (−40°C to 85°C).

Supply support for TPS54673PWPR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with over 50 years of power management innovation.

The TPS54673PWPR belongs to TI's SWIFT™ family of integrated dc/dc regulators, designed specifically for high-efficiency, high-current point-of-load conversion in space-constrained digital systems like FPGAs, DSPs, and microprocessors.

FAQ

What is the recommended PCB layout practice for thermal management of the TPS54673PWPR?

The TPS54673PWPR requires soldering its exposed PowerPAD to a dedicated analog ground plane with at least eight 0.013-inch-diameter thermal vias inside the pad area and four additional 0.018-inch vias under the package. A 3-inch × 3-inch, 1-oz copper plane is recommended for full 6-A operation at 85°C ambient. The AGND and PGND pins must connect separately to minimize ground noise coupling into the error amplifier.

Does the TPS54673PWPR support output precharge, and how does it behave during startup?

Yes, the TPS54673PWPR supports output precharge via its Disabled Sinking During Start-up (DSDS) feature. During startup, the low-side MOSFET remains off until the high-side FET reaches maximum duty cycle, preventing discharge of precharged output capacitors. This allows safe integration with upstream hold-up circuits in FPGA and DSP systems without output voltage droop.

What is the function of the SS/ENA pin on the TPS54673PWPR, and how is it configured for enable control?

The SS/ENA pin on the TPS54673PWPR serves dual functions: logic-level enable (threshold 1.2 V) and external slow-start timing. When pulled above 1.2 V, the device enables and begins internal 3.35-ms soft-start. Adding a capacitor between SS/ENA and AGND extends this ramp time linearly-approximately 0.7 V per 5 µA of charge current-allowing precise control of output voltage rise for system sequencing.

How does the TPS54673PWPR handle synchronization with external clock sources?

The TPS54673PWPR uses the SYNC pin to select between two internal frequencies (350 kHz or 550 kHz) or synchronize to an external oscillator up to 700 kHz. When synchronizing, a resistor must be connected from RT to AGND to set the internal oscillator frequency slightly below the external clock to ensure reliable locking. The SYNC pin accepts TTL/CMOS logic levels with 0.8-V low and 2.5-V high thresholds.

What protection features are integrated into the TPS54673PWPR, and how do they respond under fault conditions?

The TPS54673PWPR integrates peak current limiting (trip points 7.2–12 A depending on VIN), thermal shutdown (150°C with 10°C hysteresis), under-voltage lockout (2.95-V turn-on), and power-good monitoring (PWRGD asserts low if VSENSE falls below 90% Vref). During overcurrent, the device cycles into hiccup mode; during thermal fault, it latches off until junction temperature drops below 140°C.