Texas Instruments TPS546D24RVFR
- Part No.:
- TPS546D24RVFR
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- -
- Datasheet:
-
TPS546D24RVFR.pdf
- Description:
- IC REG CTRLR
- Quantity:
- Payment:

- Shipping:

Inventory:2,500
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS546D24RVFR from Texas Instruments is a 40-A, PMBus-enabled buck converter with 2.95-V to 16-V PVIN input range, integrated 4.5-mΩ/0.9-mΩ MOSFETs, and support for up to 4× stacking to deliver 160 A. It features differential remote sensing (<1% VOUT error over –40°C to +150°C), selectable switching frequencies (225 kHz–1.5 MHz), and operates in a 7 mm × 5 mm × 1.5 mm LQFN-CLIP (40-pin) package for high-density server and telecom power rails.
For engineers reviewing the TPS546D24RVFR datasheet, TPS546D24RVFR pinout, TPS546D24RVFR application, or TPS546D24RVFR equivalent, key selection considerations include stackable current sharing via back-channel communication, PMBus telemetry for VOUT/IOUT/die temperature, AVS/margining capability, and pin-strapped or digital output voltage configuration (0.25 V–5.5 V).
Technical Context
The TPS546D24RVFR employs fixed-frequency average current-mode control with input feedforward and selectable internal compensation, enabling stable operation across wide output capacitance ranges without external loop tuning. Its dual-rail architecture separates PVIN (power stage) and AVIN (controller), supporting split-input configurations and external 5-V biasing of VDD5 to reduce dissipation.
Back-channel communication (BCX_CLK/BCX_DAT) enables synchronized multi-phase operation with single-PMBus-address control, while VSHARE and GOSNS/SLAVE pins coordinate voltage sharing and master/slave identification in stacked configurations. The device supports prebiased startup and strongly coupled inductors for improved transient response in high-current ASIC/FPGA core supplies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | PVIN: 2.95 V–16 V; AVIN: 2.95 V–18 V - enables flexible rail partitioning and noise isolation between power stage and controller. |
| Output Current | 40 A per unit; up to 160 A with 2×–4× stacking - delivers scalable high-current capability for AI accelerators and multi-core SoCs. |
| Switching Frequency | 225 kHz–1.5 MHz (12 options, 8 pin-strappable) - allows optimization of efficiency vs. size for 4–12-layer PCBs in data center systems. |
| Output Voltage Range | 0.25 V–5.5 V via PMBus; 0.6 V–5.5 V via pin strap - supports dynamic voltage scaling for CPU/GPU cores and I/O domains. |
| VOUT Accuracy | <±1% over –40°C to +150°C TJ with differential remote sensing - ensures tight regulation at point-of-load under thermal stress. |
| Integrated MOSFETs | High-side: 4.5 mΩ; Low-side: 0.9 mΩ - reduces conduction loss and eliminates external FET layout complexity in compact 7 mm × 5 mm footprint. |
| PMBus Interface | 1-MHz clock support with full telemetry (VOUT, IOUT, die temp), AVS, margining, fault response programming - enables real-time system-level power management and diagnostics. |
Pinout & Package
TPS546D24RVFR uses a 40-pin LQFN-CLIP (RVF) package with 0.5-mm pitch, 7.0 mm × 5.0 mm body, and exposed thermal pad internally connected to PGND. Thermal pad soldering is mandatory for thermal performance and mechanical reliability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PGD/RST_B | Open-drain power-good/reset output | Signals valid VOUT or asserts reset# on fault; configurable via PMBus bit for system sequencing. |
| PMB_DATA / PMB_CLK | PMBus bidirectional data/clock | Enables standardized digital configuration and telemetry; supports 1-MHz operation for fast telemetry reads. |
| VOSNS / GOSNS/SLAVE | Differential remote sense inputs | VOSNS connects to load VOUT; GOSNS pulled high indicates slave mode - enables <1% regulation accuracy at point-of-load. |
| VSHARE | Multi-phase current-sharing bus | Carries analog voltage proportional to phase current; required for automatic current balancing in stacked configurations. |
| BCX_CLK / BCX_DAT | Back-channel synchronization interface | Coordinates timing and parameter updates across stacked units using single PMBus address - simplifies firmware design. |
| ADRSEL / MSEL1 / MSEL2 / VSEL | PMBus default configuration pins | Resistor-divider programmable for address, frequency, soft-start, OCL, and feedback divider - enables "program-free" power-up. |
| SYNC | Frequency sync I/O | Configurable as SYNC IN or SYNC OUT via ADRSEL or PMBus - allows synchronization to system clock or daisy-chained timing distribution. |
| VDD5 / BP1V5 | Internal LDO outputs | VDD5 (5 V) powers gate drivers; BP1V5 (1.5 V) powers digital logic - external 5-V bias on VDD5 improves efficiency at high load. |
Key Features
| Feature | Design Value |
|---|---|
| Stackable architecture | 2×–4× interconnection with back-channel communication enables 160-A single-rail solutions without additional address decoding logic. |
| Differential remote sensing | Compensates for PCB IR drop to maintain <1% VOUT accuracy at load, critical for sub-1V ASIC core rails. |
| Selectable internal compensation | Eliminates need for external compensation network - reduces BOM count and layout sensitivity across capacitor ESR/ESL variations. |
| Strongly coupled inductor support | Enables interleaved operation with reduced output ripple and input current harmonics - lowers bulk capacitance requirements. |
| Prebiased output startup | Allows safe power-up into precharged output capacitors - prevents reverse current flow in hot-swap or redundant supply applications. |
Applications
| Data Center Switches | Rack Servers |
|---|---|
Use Scenario: High-current 0.8-V core supply for switch ASICs with dynamic load steps exceeding 100 A/µs. IC Role / Device Role / Timing Role: Primary PMBus-configurable buck regulator delivering 40–160 A with real-time telemetry and AVS. Use Value: Stackable current sharing and differential sensing ensure stable low-voltage regulation during rapid load transients in 1U/2U platforms. | Use Scenario: Multi-phase 1.2-V GPU/FPGA core rail in AI training servers requiring coordinated voltage scaling. IC Role / Device Role / Timing Role: Synchronized stack master managing shared VSHARE and BCX signals across 4 units. Use Value: Single-PMBus-address control and AVS capability enable dynamic voltage/frequency scaling aligned with workload profiles. |
| Active Antenna Systems | Medical Imaging Equipment |
Use Scenario: Compact 3.3-V RF front-end supply in 5G massive MIMO base stations with strict EMI and thermal constraints. IC Role / Device Role / Timing Role: High-efficiency buck converter operating at 1.2 MHz with spread-spectrum sync to reduce conducted emissions. Use Value: 7 mm × 5 mm footprint and integrated MOSFETs minimize board area while maintaining >92% efficiency at 30 A. | Use Scenario: Precision 1.8-V and 2.5-V analog supply rails in MRI/CT detector modules requiring ultra-low noise and long-term stability. IC Role / Device Role / Timing Role: Remote-sensed buck regulator with <1% VOUT error over full industrial temperature range. Use Value: Differential sensing and internal 0.5% reference ensure consistent ADC/DAC performance despite PCB trace resistance drift. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-current PMBus buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPM3695-100 | 100-A rated, integrated inductor, no PMBus - uses proprietary digital interface; smaller 10 mm × 11.9 mm module footprint. | Limited to single-unit 100-A use; lacks stacking, remote sensing, and full PMBus telemetry. | Choose when board space is constrained and system-level telemetry is handled externally. |
| ISL91302B | Dual-output (2×20 A), 2.5-V–5.5-V input, I²C interface only - no PMBus command set, no VSHARE/BCX stacking. | Designed for mobile SoC power, not data center/server; lacks differential sensing and AVS. | Choose for portable applications needing dual-rail sequencing but not high-current stacking or telemetry. |
Compared with MPM3695-100 and ISL91302B, the TPS546D24RVFR uniquely combines stackable 40-A per unit, full PMBus compliance, differential remote sensing, and AVS - making it the only option for scalable, telemetry-rich, thermally demanding server and telecom core rails.
Availability
TPS546D24RVFR is available at Aetrix Electronics and suitable for data center switches, rack servers, and active antenna systems requiring stable component supply, long lifecycle support, and traceable sourcing for production programs.
Supply support for TPS546D24RVFR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and power management technologies, with decades of leadership in high-reliability power conversion ICs.
The TPS546D24RVFR belongs to TI's high-current, digitally controlled DC/DC converter product line, designed specifically for scalable, telemetry-driven power delivery in cloud infrastructure, 5G base stations, and high-performance computing systems.
FAQ
What is the maximum output current achievable with a single TPS546D24RVFR unit?
A single TPS546D24RVFR delivers up to 40 A continuous output current under thermal-limited conditions with proper PCB layout and airflow. This rating assumes operation within the specified input voltage range (2.95 V–16 V PVIN), junction temperature ≤125°C, and use of recommended external components including low-ESR output capacitors and a properly sized power inductor. The TPS546D24RVFR datasheet specifies this as the guaranteed minimum output current across temperature and line conditions.
Does the TPS546D24RVFR support differential remote voltage sensing?
Yes, the TPS546D24RVFR supports true differential remote sensing using the VOSNS and GOSNS/SLAVE pins. When configured as a loop master, VOSNS connects to the load's positive output node and GOSNS/SLAVE to the load's ground node, enabling compensation for PCB trace resistance and maintaining <1% output voltage accuracy from –40°C to +150°C junction temperature. This feature is explicitly documented in the "Differential Remote Sensing" section of the TPS546D24RVFR datasheet.
Can multiple TPS546D24RVFR devices be stacked to increase current capacity?
Yes, the TPS546D24RVFR supports 2×, 3×, or 4× stacking to deliver up to 160 A on a single output rail. Stacking is enabled by dedicated back-channel pins (BCX_CLK, BCX_DAT), voltage sharing (VSHARE), and master/slave configuration (GOSNS/SLAVE). All stacked units share a single PMBus address, and current sharing is achieved through analog VSHARE signaling - a capability confirmed in the TPS546D24RVFR product folder and datasheet "Stackable Architecture" feature description.
What is the purpose of the VDD5 pin on the TPS546D24RVFR?
The VDD5 pin on the TPS546D24RVFR is the output of an internal 5-V LDO that powers the high-side gate driver stage. It must be bypassed with ≥4.7 µF ceramic capacitance to PGND at the thermal pad. Critically, VDD5 can be overdriven with an external 5-V supply to improve efficiency and reduce power dissipation - a design option explicitly described in the TPS546D24RVFR datasheet "Description" section and validated in TI's application notes for high-current server applications.
Which PMBus commands are supported by the TPS546D24RVFR for telemetry and control?
The TPS546D24RVFR implements a comprehensive PMBus command set including VOUT_COMMAND, VOUT_OV_FAULT_LIMIT, IOUT_OC_FAULT_LIMIT, OPERATION, ON_OFF_CONFIG, VOUT_MODE, READ_VOUT, READ_IOUT, READ_TEMPERATURE_1, and MFR_SPECIFIC commands for AVS and margining. Full telemetry for output voltage, output current, and internal die temperature is supported at up to 1-MHz clock rate - details are listed in the "PMBus Command Set" table of the TPS546D24RVFR datasheet revision SLUSDJ0A.
TPS546D24RVFR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- -
- Voltage - Input:
- -
- Number of Outputs:
- -
- Voltage - Output:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
TPS546D24RVFR FAQ
1.How can I place an order for TPS546D24RVFR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS546D24RVFR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS546D24RVFR reliable?
The price and inventory of TPS546D24RVFR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS546D24RVFR is usually 5 days.
3.What payment methods are accepted for TPS546D24RVFR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS546D24RVFR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS546D24RVFR?
TPS546D24RVFR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS546D24RVFR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS546D24RVFR?
For technical support, including TPS546D24RVFR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS546D24RVFR requirements.
6.How does Aetrix verify that TPS546D24RVFR is sourced from the original manufacturer or authorized distributors?
All TPS546D24RVFR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS546D24RVFR meets industry standards.
7.What is the process for return or replacement of TPS546D24RVFR?
All TPS546D24RVFR units undergo pre-shipment inspection (PSI). If there is an issue with TPS546D24RVFR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS546D24RVFR part is unused and in its original packaging.
Return procedure for TPS546D24RVFR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS546D24RVFR Tags

-
TPS51206DSQR
Texas Instruments

-
TPS51200DRCR
Texas Instruments

-
TPS51200DRCT
Texas Instruments

-
TPS62740DSSR
Texas Instruments

-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi

-
RT9026GSP
Richtek USA Inc.

-
LP2998MRX/NOPB
Texas Instruments

-
TPS51200QDRCRQ1
Texas Instruments

-
DPA423GN-TL
Power Integrations

-
LM10011SD/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

