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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Special Purpose Regulators

Texas Instruments TPS54872PWP

Name: TPS54872PWP
Brand: Texas Instruments
SKU: TPS54872PWP
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TPS54872PWP

Manufacturer:: Texas Instruments

Category:: Special Purpose Regulators

Package:: 28-PowerTSSOP (0.173", 4.40mm Width)

Datasheet:: TPS54872PWP.pdf

Description:: IC REG CONV DDR 1OUT 28HTSSOP

Quantity:: RFQ Add To RFQ list

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Product details

Overview

TPS54872PWP from Texas Instruments is a synchronous-buck PWM DC/DC converter optimized for high-current DDR memory termination and precision point-of-load regulation. It delivers up to 8 A continuous output current with 30 mΩ high-side and low-side MOSFETs, supports 280–700 kHz adjustable switching frequency (or fixed 350 kHz), operates from 4–6 V input, and tracks external reference voltages from 0.2 V to 1.75 V - enabling precise 1.25 V VTTQ generation in DDR systems.

For engineers reviewing the TPS54872PWP datasheet, TPS54872PWP pinout, TPS54872PWP application, or TPS54872PWP equivalent, this device is selected for high-efficiency, thermally robust, low-noise power delivery in DDR termination, GTL/SSTL active termination, DAC-controlled current stages, and precision PoL supplies where tight load/line regulation (<0.03%/A, <0.04%/V), fast transient response, and integrated thermal protection are required.

Technical Context

The TPS54872PWP implements a voltage-mode synchronous buck architecture with an internal high-performance error amplifier (90–110 dB open-loop gain, 3–5 MHz unity-gain bandwidth), adaptive dead-time control, and cycle-by-cycle peak current limiting. Its dual-ground design separates AGND (for compensation, REFIN, RT, VBIAS) from PGND (high-current return for VIN, PH, and output filter), minimizing noise coupling in sensitive feedback paths.

It integrates a 2.8 V internal bias regulator (VBIAS), under-voltage lockout (UVLO start at 3.80 V, hysteresis 0.16 V), and internal slow-start (2.6–4.1 ms). The PH node connects to 9 parallel pins for low-inductance, high-current phase routing, while BOOT drives the high-side FET via an external 0.022–0.1 µF capacitor referenced to PH.

Key Specifications

Parameter	Value and Actual Design Meaning
Input Voltage Range	4 V to 6 V - matches standard DDR supply rails (e.g., 5 V nominal) and ensures stable operation across industrial temperature range.
Continuous Output Current	8 A source/sink - supports full DDR memory bus termination loads without external current boosting.
MOSFET rDS(on)	30 mΩ (VI = 4.5 V) - enables >90% efficiency at 8 A (measured), reducing thermal stress and eliminating need for heatsinks.
Switching Frequency	Fixed 350 kHz or adjustable 280–700 kHz via RT resistor - allows optimization of inductor size, EMI profile, and transient response.
Output Voltage Tracking Range	6% to 90% of VI - supports precise tracking of half-VDDQ (e.g., 1.25 V from 2.5 V) for DDR VTT applications.
Load Regulation	0.03 %/A - maintains ±0.24 mV output deviation over 0–8 A load step, critical for DDR signal integrity.
Thermal Shutdown Trip	135–165 °C - protects against sustained overload; 10 °C hysteresis enables automatic recovery after fault clearance.

Pinout & Package

TPS54872PWP is housed in a thermally enhanced 28-pin HTSSOP (PWP) PowerPAD^® package measuring 6.4 mm × 9.7 mm, with an exposed thermal pad soldered directly to PCB for efficient heat dissipation (θ_JA = 14.4 °C/W with solder).

Pin/Terminal	Circuit Role	Design Meaning
AGND (Pin 1)	Analog ground reference	Return path for compensation network, REFIN, RT, VBIAS, and SYNC; must be isolated from PGND except at single-point connection.
VSENSE (Pin 2)	Error amplifier inverting input	Connects to output voltage divider; senses regulated output with 60–250 nA input bias current for minimal loading.
COMP (Pin 3)	Error amplifier output	Drives external Type 2/3 compensation network; slew rate 1.0–1.4 V/µs enables wide closed-loop bandwidth (80–125 kHz crossover).
STATUS (Pin 4)	Open-drain power-good indicator	Asserts low during UVLO, VBIAS undervoltage, or thermal shutdown; sinks 2.5 mA max with 0.18–0.30 V saturation voltage.
BOOT (Pin 5)	Bootstrap driver supply	Connects to PH via 0.022–0.1 µF ceramic capacitor; powers high-side gate driver with internal 2.5 Ω bootstrap switch.
PH (Pins 6–14)	Phase node (switching node)	9 parallel pins reduce inductance and current density; connects directly to output inductor and boot capacitor - requires minimal loop area.
RT (Pin 28)	Oscillator frequency setting	Resistor to AGND sets frequency: floating = 350 kHz; 68–180 kΩ = 280–700 kHz - enables EMI tuning and layout flexibility.
ENA (Pin 27)	Enable control input	Logic-high threshold 0.82–1.40 V; disables oscillator, PWM, and drivers when low, reducing quiescent current to 1–1.4 mA.
REFIN (Pin 26)	External reference input	High-impedance (nA-level) input accepts 0.2–1.75 V tracking voltage (e.g., half-VDDQ); overrides internal 0.8 V reference when valid.
VBIAS (Pin 25)	Internal bias regulator output	Supplies 2.70–2.90 V to internal circuitry; bypassed with 0.1–1.0 µF ceramic capacitor to AGND for stability and noise immunity.
VIN (Pins 20–24)	Main power input	5 parallel pins accept 4–6 V input; require local 10 µF ceramic bypass to PGND with minimized loop area to suppress ripple.
PGND (Pins 15–19)	Power ground return	High-current return for low-side FET and input/output capacitors; must connect to large copper areas and separate from AGND plane.

Key Features

Feature	Design Value
Integrated 30 mΩ MOSFETs	Eliminates external power switches and reduces board area by >40% versus discrete solutions while maintaining >90% efficiency at 8 A.
True voltage-mode error amplifier	90–110 dB open-loop gain and 3–5 MHz unity-gain bandwidth enable stable compensation with wide L/C selection - no mandatory external components.
Adaptive dead-time control	Prevents shoot-through by sequencing high-side turn-on only after low-side gate falls below 2 V, and vice versa - improves reliability at high switching frequencies.
Tracking reference input (REFIN)	Accepts 0.2–1.75 V external voltage (e.g., DDR VDDQ/2) to precisely regulate VTTQ without resistive divider errors or drift.
PowerPAD^® thermal interface	Exposed thermal pad soldered to PCB provides 14.4 °C/W junction-to-ambient thermal resistance - sustains 8 A continuous operation without heatsink at TA ≤ 70 °C.

Applications

DDR Memory Termination Voltage	Active Termination of GTL/SSTL Logic
Use Scenario: Providing matched, low-noise termination voltage (VTT) for DDR2/DDR3 memory buses operating at 1.25 V with dynamic load currents up to ±8 A. IC Role / Device Role / Timing Role: Synchronous buck regulator sourcing and sinking current to maintain VTT at exactly half of VDDQ during read/write transitions. Use Value: Achieves ±0.24 mV load regulation and <20 mV output ripple, ensuring signal integrity and compliance with JEDEC DDR timing margins.	Use Scenario: Supplying dynamically adjusted termination voltage for high-speed GTL+ and SSTL-2 logic families in server backplanes and FPGA I/O banks. IC Role / Device Role / Timing Role: Precision tracking regulator that follows a buffered reference derived from core I/O supply, compensating for rail droop and temperature drift. Use Value: Delivers 8 A sink/source capability with 2.6–4.1 ms controlled ramp, preventing overshoot/undershoot during hot-swap or power sequencing events.
DAC-Controlled High-Current Output Stage	Precision Point-of-Load Power Supply
Use Scenario: Generating programmable, high-current bias voltage for RF power amplifiers or laser diode drivers using a DAC output as REFIN. IC Role / Device Role / Timing Role: Adjustable-output buck converter with 0.2–1.75 V reference input range, enabling direct DAC-to-VOUT mapping without op-amp buffering. Use Value: Maintains 0.03 %/A load regulation and 0.04 %/V line regulation - preserves DAC resolution across full current range and input variation.	Use Scenario: Delivering tightly regulated 1.25 V at up to 8 A to ASICs, DSPs, or FPGAs in industrial control and telecom equipment. IC Role / Device Role / Timing Role: Primary PoL regulator with integrated MOSFETs, thermal shutdown, and status flag for system monitoring and fault logging. Use Value: Integrates all active power-stage components into a single 6.4 × 9.7 mm footprint, reducing BOM count by 12+ parts versus controller + external FET solution.

DDR Memory Termination Voltage

Active Termination of GTL/SSTL Logic

Use Scenario: Providing matched, low-noise termination voltage (VTT) for DDR2/DDR3 memory buses operating at 1.25 V with dynamic load currents up to ±8 A.

IC Role / Device Role / Timing Role: Synchronous buck regulator sourcing and sinking current to maintain VTT at exactly half of VDDQ during read/write transitions.

Use Value: Achieves ±0.24 mV load regulation and <20 mV output ripple, ensuring signal integrity and compliance with JEDEC DDR timing margins.

Use Scenario: Supplying dynamically adjusted termination voltage for high-speed GTL+ and SSTL-2 logic families in server backplanes and FPGA I/O banks.

IC Role / Device Role / Timing Role: Precision tracking regulator that follows a buffered reference derived from core I/O supply, compensating for rail droop and temperature drift.

Use Value: Delivers 8 A sink/source capability with 2.6–4.1 ms controlled ramp, preventing overshoot/undershoot during hot-swap or power sequencing events.

DAC-Controlled High-Current Output Stage

Precision Point-of-Load Power Supply

Use Scenario: Generating programmable, high-current bias voltage for RF power amplifiers or laser diode drivers using a DAC output as REFIN.

IC Role / Device Role / Timing Role: Adjustable-output buck converter with 0.2–1.75 V reference input range, enabling direct DAC-to-VOUT mapping without op-amp buffering.

Use Value: Maintains 0.03 %/A load regulation and 0.04 %/V line regulation - preserves DAC resolution across full current range and input variation.

Use Scenario: Delivering tightly regulated 1.25 V at up to 8 A to ASICs, DSPs, or FPGAs in industrial control and telecom equipment.

IC Role / Device Role / Timing Role: Primary PoL regulator with integrated MOSFETs, thermal shutdown, and status flag for system monitoring and fault logging.

Use Value: Integrates all active power-stage components into a single 6.4 × 9.7 mm footprint, reducing BOM count by 12+ parts versus controller + external FET solution.

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck regulator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS54672PWP	Same PWP package and pinout; higher current limit (12 A vs. 11 A typical), identical 30 mΩ MOSFETs, same REFIN tracking range and UVLO thresholds.	Targeted for higher-current DDR4 termination and multi-phase PoL designs requiring >8 A per phase.	Select TPS54672PWP when 12 A peak current headroom or tighter thermal margin is required; otherwise TPS54872PWP offers optimal cost/performance for 8 A DDR3/VTT.
TPS54372PWP	Same family, PWP package, and REFIN tracking; lower continuous output (3 A), smaller 16-pin HTSSOP package, reduced MOSFET rDS(on) (22 mΩ), no PH pin paralleling.	Suitable for low-power DDR termination, small-form-factor PoL, or auxiliary rails where space and current demand are constrained.	Choose TPS54372PWP for compact 3 A applications; avoid for 8 A loads due to thermal and current-limit limitations - not a drop-in replacement.

Compared with TPS54672PWP and TPS54372PWP, the TPS54872PWP uniquely balances 8 A continuous capability, 28-pin thermal-optimized layout, and full DDR VTT tracking functionality - making it the designated solution for mid-range DDR3 termination and precision 1.25 V PoL where cost, thermal performance, and feature completeness intersect.

Availability

TPS54872PWP is available at Aetrix Electronics and suitable for DDR memory termination, GTL/SSTL active termination, and precision point-of-load power supplies requiring stable component supply, long-term lifecycle support, and traceable sourcing for industrial and embedded OEM programs.

Supply support for TPS54872PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power conversion ICs.

The TPS54872PWP belongs to TI's SWIFT™ family of integrated DC/DC regulators, designed specifically for high-current, low-voltage point-of-load applications in computing, communications, and industrial systems demanding efficiency, thermal robustness, and fast transient response.

FAQ

What is the maximum continuous output current supported by the TPS54872PWP?

The TPS54872PWP supports 8 A continuous output current in both sourcing and sinking modes, verified across −40°C to 125°C junction temperature with proper PCB thermal design (e.g., PowerPAD soldered to ≥3″×3″ 1 oz copper plane). This rating assumes operation within recommended conditions: VI = 4–6 V, fs ≤ 700 kHz, and adequate heatsinking per SLMA002 guidelines. The device includes cycle-by-cycle current limiting (9–11 A trip) and thermal shutdown for overload protection.

Does the TPS54872PWP support external frequency adjustment, and how is it configured?

Yes, the TPS54872PWP supports externally adjustable switching frequency from 280 kHz to 700 kHz using a resistor connected between the RT pin (Pin 28) and AGND. A floating RT pin defaults to 350 kHz. For example, a 71.5 kΩ resistor sets 700 kHz, while 68 kΩ and 180 kΩ yield ~700 kHz and ~280 kHz respectively. The relationship is approximated by f_sw ≈ 500 kHz × (100 kΩ / R), with actual values varying ±10% due to process tolerance.

How does the REFIN pin function in the TPS54872PWP, and what voltage range is acceptable?

The REFIN pin (Pin 26) is a high-impedance input (60–250 nA bias current) that accepts an external tracking voltage from 0.2 V to 1.75 V. When valid, it overrides the internal 0.8 V reference and sets the output voltage to match the REFIN level - enabling precise DDR VTT generation (e.g., 1.25 V from half-VDDQ). Voltages above 1.75 V default to the internal reference; below 0.2 V disable regulation. No external buffer is required due to its high input impedance.

What thermal management features does the TPS54872PWP include, and how is the PowerPAD used?

The TPS54872PWP integrates thermal shutdown (trip: 135–165 °C, hysteresis: 10 °C) and relies on its exposed PowerPAD (Pin 0) for conduction cooling. The PowerPAD must be soldered to a dedicated AGND-connected copper area with ≥8 × 0.013″ vias inside the pad and 4 × 0.018″ vias under the package. With proper layout, thermal resistance drops to 14.4 °C/W (junction-to-ambient), enabling 8 A operation at TA ≤ 70 °C without additional heatsinking.

Can the TPS54872PWP sink current, and in which applications is this capability utilized?

Yes, the TPS54872PWP is a bidirectional synchronous buck capable of continuous current sinking - essential for DDR VTT termination, where current flows from memory lines into the regulator during read cycles. It maintains regulation during sink operation using the same current-limit and thermal protection mechanisms. This capability eliminates the need for external sinking circuits and ensures balanced rise/fall transient response, as validated in Figure 17 (source-sink transient response).

TPS54872PWP Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: SWIFT™

Package/Case:: 28-PowerTSSOP (0.173", 4.40mm Width)

Packaging:: Bulk

Product Status:: Active

Applications:: Converter, DDR

Voltage - Input:: 4V ~ 6V

Number of Outputs:: 1

Voltage - Output:: 0.2V ~ 3.3V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 28-HTSSOP

TPS54872PWP FAQ

1.How can I place an order for TPS54872PWP through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS54872PWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS54872PWP reliable?

The price and inventory of TPS54872PWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54872PWP is usually 5 days.

3.What payment methods are accepted for TPS54872PWP?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54872PWP transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TPS54872PWP?

TPS54872PWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS54872PWP order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS54872PWP?

For technical support, including TPS54872PWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54872PWP requirements.

6.How does Aetrix verify that TPS54872PWP is sourced from the original manufacturer or authorized distributors?

All TPS54872PWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54872PWP meets industry standards.

7.What is the process for return or replacement of TPS54872PWP?

All TPS54872PWP units undergo pre-shipment inspection (PSI). If there is an issue with TPS54872PWP, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS54872PWP part is unused and in its original packaging.

Return procedure for TPS54872PWP:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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