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Texas Instruments TPS54873PWPR
- Part No.:
- TPS54873PWPR
- Manufacturer:
- Texas Instruments
- Package:
- 28-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS54873PWPR.pdf
- Description:
- IC REG BUCK ADJ 8A 28HTSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,664
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Product details
Overview
TPS54873PWPR from Texas Instruments is a 4-V to 6-V input, 8-A synchronous buck PWM converter in a thermally enhanced 28-pin HTSSOP (PWP) PowerPAD™ package. It integrates high-side and low-side 30-mΩ MOSFETs, delivers 0.9-V to 3.3-V adjustable output with 1.0% reference accuracy, operates at fixed 350 kHz or 550 kHz or adjustable 280–700 kHz, and disables sinking current during startup to prevent output precharge droop - used for point-of-load regulation in FPGAs and DSPs.
For engineers reviewing the TPS54873PWPR datasheet, TPS54873PWPR pinout, TPS54873PWPR application, or TPS54873PWPR equivalent, key selection criteria include its 8-A continuous sourcing capability without startup sinking, thermal performance enabled by PowerPAD™ soldering, 3.35-ms internal slow-start, UVLO with 3.85-V turn-on threshold, and compatibility with external frequency synchronization up to 700 kHz.
Technical Context
The TPS54873PWPR implements a voltage-mode PWM control architecture with an integrated high-performance error amplifier (110 dB open-loop gain, 5 MHz unity-gain bandwidth) and adaptive dead-time logic. Its oscillator supports three configuration modes: internally fixed (350/550 kHz), externally resistor-set (280–700 kHz via RT pin), or synchronized to external clock (330–700 kHz via SYNC pin).
Startup behavior is defined by disabled low-side FET conduction until maximum duty cycle is reached - eliminating sink current into precharged outputs. Protection includes peak current limiting (10 A typical trip), thermal shutdown (150°C nominal), and power-good monitoring with 90% Vref threshold and 3% hysteresis.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.0 V to 6.0 V - supports standard 5-V rail with 0.2-V margin before UVLO activation |
| Continuous Output Current | 8 A - sustained sourcing only; sinking disabled during startup prevents precharge collapse |
| Output Voltage Accuracy | ±1.0% over temperature - achieved via factory-trimmed 0.891-V reference and precision error amplifier |
| Switching Frequency | Adjustable 280–700 kHz - set by RT resistor or synchronized externally; enables EMI optimization and inductor size reduction |
| High-Side rDS(on) | 30 mΩ at 4.5 V VIN - contributes to >90% efficiency at 5-V input / 3.3-V / 8-A output per Figure 12 |
| Thermal Resistance θJA | 18.2 °C/W with soldered PowerPAD™ - enables full 8-A operation at TA ≤ 70°C on standard 4-layer PCB |
| Startup Delay | 3.35 ms internal slow-start - linear ramp of internal reference ensures controlled output rise without inrush |
Pinout & Package
The TPS54873PWPR is housed in a 28-pin HTSSOP (PWP) package with exposed PowerPAD™ thermal pad requiring solder connection to AGND plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND (Pin 1) | Analog ground reference | Return for compensation network, VSENSE divider, SS/ENA capacitor, and RT resistor; must connect to PowerPAD™ |
| VSENSE (Pin 2) | Error amplifier inverting input | Monitors output voltage via resistive divider; sets regulation point with 0.891-V internal reference |
| COMP (Pin 3) | Error amplifier output | Drives external Type-3 compensation network between COMP and VSENSE for loop stability |
| PWRGD (Pin 4) | Open-drain power-good indicator | Asserts high when VSENSE ≥ 90% Vref; used for processor reset or supply sequencing |
| BOOT (Pin 5) | Bootstrap gate drive supply | Connects to PH node via 0.022–0.1-µF ceramic capacitor to enable high-side MOSFET drive |
| PH (Pins 6–14) | Phase node | Internal switch node connecting high/low-side MOSFETs and external output inductor; requires minimized trace area |
| RT (Pin 28) | Frequency setting input | Resistor-to-AGND sets free-running frequency; required for SYNC-based synchronization |
| SS/ENA (Pin 26) | Enable and slow-start control | Logic-high (>1.2 V) enables operation; external capacitor extends soft-start time beyond 3.35 ms |
| SYNC (Pin 27) | Frequency synchronization input | Accepts external clock (330–700 kHz); selects internal 350/550 kHz when held low/high |
| VBIAS (Pin 25) | Internal bias regulator output | Supplies 2.8-V ±0.1-V regulated voltage to internal circuitry; bypass with 0.1–1.0-µF ceramic to AGND |
| VIN (Pins 20–24) | Main power input | Supplies MOSFET switches and internal LDO; requires local 10-µF ceramic bypass to PGND |
| PGND (Pins 15–19) | Power ground return | High-current return path for low-side FET and input/output capacitors; separate from AGND |
Key Features
| Feature | Design Value |
|---|---|
| Disabled sinking during startup (DSDS) | Prevents discharge of precharged output capacitors - critical for systems where upstream supplies power the output before regulation begins |
| Integrated 30-mΩ MOSFETs | Enables compact 8-A design without external power stages; eliminates gate driver complexity and layout sensitivity |
| PowerPAD™ thermal package | Reduces θJA to 18.2 °C/W with proper PCB layout - allows full-rated current without heatsink on industrial-grade boards |
| Programmable switching frequency | Supports EMI compliance via spread-spectrum-like frequency selection and inductor size optimization across 280–700 kHz range |
| True voltage-mode control | Uses high-gain, wide-bandwidth error amplifier (90–110 dB, 3–5 MHz) for precise line/load regulation and stable loop compensation |
Applications
| FPGA Core Supply | DSP I/O Rail Regulation |
|---|---|
Use Scenario: Powers 0.9-V core of Xilinx Kintex-7 FPGA during configuration and steady-state operation, with fast transient response to logic switching. IC Role / Device Role / Timing Role: Primary synchronous buck regulator delivering tightly regulated 0.9-V @ 8-A with <1% output deviation under 4-A step load. Use Value: DSDS prevents core voltage collapse during hot-plug or partial power-up sequences where board capacitance is precharged by auxiliary rails. |
Use Scenario: Supplies 3.3-V I/O bank for TI C6678 multicore DSP, supporting simultaneous DDR3 interface and PCIe signaling. IC Role / Device Role / Timing Role: High-current point-of-load converter with PWRGD signal coordinated to DSP reset timing and boot sequence. Use Value: 3.35-ms slow-start aligns with DSP's internal power-on reset window; 550-kHz switching minimizes output filter footprint near dense BGA packages. |
| Optical Line Card DC/DC | PowerPC Processor Supply |
Use Scenario: Generates 1.2-V, 6-A supply for TI TMS320C6455 DSP in telecom line cards operating in NEBS-compliant enclosures. IC Role / Device Role / Timing Role: Input-filtered buck stage converting 5-V backplane to DSP core voltage; synchronized to system clock to reduce conducted EMI. Use Value: SYNC pin enables 500-kHz operation locked to 10-MHz system clock harmonics, easing EMC filtering requirements in space-constrained modules. |
Use Scenario: Provides 1.0-V core voltage for Freescale MPC8641D dual-core PowerPC in network router control plane. IC Role / Device Role / Timing Role: Primary core regulator with UVLO set to 3.85 V to ensure clean startup after 5-V rail stabilizes post-power-cycle. Use Value: 1.0% reference accuracy maintains CPU timing margins across −40°C to 85°C; thermal shutdown protects against airflow failure in sealed chassis. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54821RHLR | Same PWP package, 20-V max input, 8-A output, but uses current-mode control and lacks DSDS feature | Requires external circuitry to manage precharge; better suited for higher-input-voltage systems (e.g., 12-V intermediate bus) | Select when input exceeds 6 V or current-mode loop stability is preferred over voltage-mode precision |
| LM27402SDX/NOPB | 6-V max input, 10-A output, external MOSFETs, no integrated power stage; supports programmable DCM/CCM modes | Higher design flexibility but increases BOM count and layout complexity; no DSDS implementation | Select when thermal constraints require discrete FETs or when dynamic mode control (e.g., light-load efficiency tuning) is mandatory |
Compared with TPS54873PWPR, TPS54821RHLR offers wider input range but sacrifices startup sinking suppression, while LM27402SDX/NOPB trades integration for configurability - making TPS54873PWPR optimal for space-constrained, precharge-sensitive 5-V input systems demanding guaranteed 8-A sourcing.
Availability
TPS54873PWPR is available at Aetrix Electronics and suitable for FPGA core supplies, DSP I/O rails, optical line card power, and PowerPC processor regulation requiring stable component supply, long-term lifecycle support, and consistent thermal performance across industrial temperature ranges.
Supply support for TPS54873PWPR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion and SWIFT™ technology.
The TPS54873PWPR belongs to TI's SWIFT™ family of integrated synchronous buck regulators, designed specifically for high-density, low-voltage point-of-load applications in communications, computing, and industrial systems where startup reliability and thermal efficiency are critical.
FAQ
What is the purpose of the DSDS (Disabled Sinking During Startup) feature in the TPS54873PWPR?
The DSDS feature in the TPS54873PWPR disables the low-side MOSFET during initial startup to prevent current sinking from precharged output capacitors. This avoids output voltage droop when upstream supplies or hold-up capacitors already charge the output before regulation begins - a critical requirement in hot-swap and multi-rail sequencing systems. The TPS54873PWPR resumes normal buck operation only after reaching maximum duty cycle.
Can the TPS54873PWPR be synchronized to an external clock, and what is the supported frequency range?
Yes, the TPS54873PWPR supports external synchronization via the SYNC pin across 330 kHz to 700 kHz. To enable synchronization, a resistor must be connected from the RT pin to AGND to set the free-running frequency near the target sync frequency (e.g., 80% of sync rate). The TPS54873PWPR will lock to the external clock within this band, reducing EMI peaks and enabling system-level timing coordination.
What is the recommended thermal layout for the TPS54873PWPR's PowerPAD™ in a 28-pin PWP package?
The TPS54873PWPR requires soldering its exposed PowerPAD™ to a dedicated AGND copper plane using eight 0.013-inch-diameter vias inside the pad area and four 0.018-inch vias under the package perimeter. A minimum 3-inch × 3-inch, 1-oz copper analog ground plane is recommended for full 8-A operation at 70°C ambient. The TPS54873PWPR's thermal performance depends entirely on this layout - insufficient vias or isolated pads cause immediate thermal shutdown.
How does the TPS54873PWPR's slow-start function interact with the SS/ENA pin and internal timing?
The TPS54873PWPR provides 3.35-ms internal slow-start by linearly ramping its 0.891-V reference voltage. When an external capacitor is added from SS/ENA to AGND, it extends startup time beyond 3.35 ms - delay ≈ C × 1.2 V / 5 µA, then ramp ≈ C × 0.7 V / 5 µA. The TPS54873PWPR holds the low-side FET off throughout slow-start, ensuring only sourcing behavior until regulation is established.
What are the absolute maximum ratings for the PH pin of the TPS54873PWPR, and why is this critical for layout?
The PH pin of the TPS54873PWPR has an absolute maximum rating of −0.6 V to +10 V. This negative limit reflects the risk of shoot-through or body-diode conduction during dead-time transitions. Layout must minimize parasitic inductance on the PH trace - long or narrow traces increase voltage spikes during switching, potentially violating the −0.6-V lower limit and damaging the internal high-side MOSFET. The TPS54873PWPR's PH pins (6–14) must be shorted together and routed directly to the inductor with minimal loop area.
TPS54873PWPR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™
- Package/Case:
- 28-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 0.9V
- Voltage - Output (Max):
- 3.3V
- Current - Output:
- 8A
- Frequency - Switching:
- 350kHz, 550kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-HTSSOP
TPS54873PWPR FAQ
1.How can I place an order for TPS54873PWPR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54873PWPR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54873PWPR reliable?
The price and inventory of TPS54873PWPR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54873PWPR is usually 5 days.
3.What payment methods are accepted for TPS54873PWPR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54873PWPR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54873PWPR?
TPS54873PWPR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54873PWPR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54873PWPR?
For technical support, including TPS54873PWPR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54873PWPR requirements.
6.How does Aetrix verify that TPS54873PWPR is sourced from the original manufacturer or authorized distributors?
All TPS54873PWPR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54873PWPR meets industry standards.
7.What is the process for return or replacement of TPS54873PWPR?
All TPS54873PWPR units undergo pre-shipment inspection (PSI). If there is an issue with TPS54873PWPR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54873PWPR part is unused and in its original packaging.
Return procedure for TPS54873PWPR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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