Texas Instruments TPS548B27RYLR
- Part No.:
- TPS548B27RYLR
- Manufacturer:
- Texas Instruments
- Package:
- 19-PowerTFQFN
- Datasheet:
-
TPS548B27RYLR.pdf
- Description:
- IC REG BUCK ADJ 20A 19VQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS548B27RYLR from Texas Instruments is a 20-A synchronous buck converter with D-CAP3™ control, differential remote sense, and integrated 7.7-mΩ/2.4-mΩ MOSFETs. It operates from 2.7 V to 16 V input, delivers 0.6 V to 5.5 V output, and features hiccup current limiting and a 3-V internal LDO - optimized for high-density server point-of-load regulation.
For engineers reviewing the TPS548B27RYLR datasheet, TPS548B27RYLR pinout, TPS548B27RYLR application, or TPS548B27RYLR equivalent, key selection considerations include its adaptive on-time D-CAP3 architecture, ±1% reference accuracy over –40°C to +125°C, programmable 600/800/1000 kHz switching, remote-sense-enabled load regulation, and 4-mm × 3-mm VQFN-FCRLF (19-pin) thermal performance.
Technical Context
The TPS548B27RYLR implements D-CAP3™ control with emulated current sensing, eliminating external compensation while supporting all-ceramic output capacitors. Its adaptive on-time modulation maintains stable frequency across wide VIN/VOUT ranges and enables ultra-fast load-step response without phase-margin tuning.
Differential remote sensing provides 0.6-V ±1% internal reference with dedicated VSNS+ and VSNS– terminals, enabling precise load regulation in high-current PCB traces. The device integrates a 3-V internal LDO (with external bias support from 3.13 V to 3.6 V), hiccup-mode OCP/UVP/OVP protection, and programmable soft-start via SS/REFIN capacitor.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7 V to 16 V (supports 20-A operation with external VCC bias); 4 V to 16 V (20-A with internal LDO) |
| Output Voltage Range | 0.6 V to 5.5 V (set via FB resistor divider; ±1% reference accuracy over full –40°C to +125°C junction range) |
| Continuous Output Current | 20 A (enabled by integrated 7.7-mΩ high-side and 2.4-mΩ low-side MOSFETs; no external heatsink required in typical layouts) |
| Switching Frequency | 600 / 800 / 1000 kHz (pin-selectable via MODE resistor; supports FCCM or Eco-mode skip for light-load efficiency) |
| Control Architecture | D-CAP3™ with adaptive on-time (no external compensation needed; stable with all ceramic output capacitors) |
| Thermal Performance | RθJA = 49.0°C/W (RYL package); RθJB = 9.2°C/W - validated for 20-A operation at ≤75°C ambient with 400 LFM airflow |
| Protection Features | Hiccup-mode OCP (programmable via TRIP resistor), output OVP/UVP, thermal shutdown (150°C trip, 30°C hysteresis), and UVLO on VIN and VCC |
Pinout & Package
TPS548B27RYLR uses a 4.00 mm × 3.00 mm, 19-pin VQFN-FCRLF (RYL) package with exposed thermal pad. Pin 1 is BOOT; pins 10–15 are PGND (six parallel power ground terminals); pins 9 and 18 are VIN; pin 16 is VCC; pin 17 is SW; pins 5 and 19 are VSNS+ and VSNS– respectively; pin 6 is FB; pin 8 is open-drain PGOOD.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BOOT (19) | High-side gate driver boost supply | Connect 0.1-µF ceramic capacitor between BOOT and SW to sustain high-side FET drive during duty cycles >90% |
| TRIP (2) | Current limit threshold setting | Resistor to AGND sets OCP trip point; ±1% tolerance recommended for accurate 20-A current limiting |
| MODE (3) | Frequency and operating mode selection | Resistor to AGND selects 600/800/1000 kHz and FCCM vs. Eco-mode; enables adaptive on-time tracking |
| SS/REFIN (4) | Soft-start timing / external reference input | Capacitor to VSNS– sets soft-start time (min 1.5 ms); external DC voltage overrides internal 0.6-V reference for tracking |
| VSNS– (5) | Remote sense return / reference ground | Connect to load ground for differential sensing; short to AGND for single-point feedback configuration |
| FB (6) | Output voltage feedback input | Resistor divider from VOUT to VSNS– sets output; internal 0.6-V ±1% reference enables <±1% load regulation accuracy |
| EN (7) | Enable control input | Logic-high >1.22 V enables converter; internal 6.5-MΩ pulldown ensures default-disable state when floating |
| PGOOD (8) | Power-good status output | Open-drain signal asserts high after 1.33-ms delay when FB is within 92.5–116% of target; sinks 17 mA at 0.4 V |
| VIN (9,18) | Main input power supply | Two dedicated input pins minimize IR drop; decouple each to adjacent PGND with ≥22-µF ceramic capacitance |
| VCC (16) | Internal LDO output / external bias input | Supplies internal circuitry and gate drivers; accepts 3.13–3.6 V external bias to bypass LDO losses and improve efficiency |
| SW (17) | Power switch node | Connects to output inductor; requires low-inductance layout to minimize EMI and switching losses |
Key Features
| Feature | Design Value |
|---|---|
| D-CAP3™ adaptive on-time control | Enables stable regulation with zero external compensation components and full compatibility with low-ESR ceramic output capacitors |
| Differential remote sensing (VSNS+/VSNS–) | Compensates for PCB trace IR drop to maintain ±1% output accuracy at the load under 20-A dynamic current steps |
| Integrated 7.7-mΩ/2.4-mΩ MOSFET pair | Supports 20-A continuous output without external FETs or heatsinks; reduces BOM count and layout area in space-constrained servers |
| Programmable hiccup current limiting | TRIP pin allows precise OCP threshold setting (e.g., 20 A ±5%) with automatic recovery after fault clearance |
| Auto-skip Eco-mode | Improves light-load efficiency to >85% at 10-mA output while maintaining tight regulation via valley-current detection |
| Prebiased start-up capability | Allows safe startup into precharged output rails without reverse current flow - critical for hot-swap and multi-rail sequencing |
Applications
| Rack Server Point-of-Load | Data Center Switch ASIC Supply |
|---|---|
Use Scenario: Regulating 0.8–1.2 V core voltage for dual-socket Xeon Scalable processors in 1U/2U rack servers. IC Role / Device Role / Timing Role: Primary 20-A buck converter with remote sense, delivering tightly regulated CPU VDDQ under fast 10-A/µs load transients. Use Value: D-CAP3™ control achieves <50-ns response to 50% load steps; ±1% remote-sense accuracy prevents processor throttling due to trace IR drop. |
Use Scenario: Powering 1.8-V or 3.3-V SerDes and packet buffer rails in 100-GbE line cards with strict ripple and transient requirements. IC Role / Device Role / Timing Role: High-efficiency, low-noise buck regulator with programmable soft-start and PGOOD sequencing for multi-rail power-up. Use Value: 800-kHz FCCM operation minimizes output ripple (<15 mVpp at 20 A); hiccup OCP prevents latch-up during cable fault events. |
| Hardware Accelerator Card (FPGA/GPU) | Industrial PC Power Management |
Use Scenario: Delivering 0.9–1.1 V at up to 20 A to FPGA fabric or AI inference accelerators with dynamic power profiles. IC Role / Device Role / Timing Role: Adaptive on-time buck converter with prebias start-up and differential sensing for reliable hot-plug operation. Use Value: Prebiased start-up avoids reverse current into charged output caps; remote sense maintains <±10 mV regulation at FPGA ball grid. |
Use Scenario: Providing robust 5-V or 3.3-V system rails in fanless industrial PCs operating from 12-V DC input in extended temperature environments. IC Role / Device Role / Timing Role: Thermally efficient buck regulator with 150°C thermal shutdown and –40°C to +125°C guaranteed operation. Use Value: RθJB = 9.2°C/W enables 20-A operation without forced air; hiccup OCP and UVLO protect against brownouts in factory-floor power systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS548B22RMLR | Same 4×3-mm VQFN-FCRLF package and D-CAP3™ control, but rated for 15-A continuous output and 0.5–5.5-V output range | Limited to lower-current loads; lacks hiccup OCP - uses constant-current foldback instead | Select when 15-A capacity suffices and hiccup recovery is not required; footprint-compatible upgrade path if current demand increases |
| MP2964GQKT-Z | Monolithic 20-A buck with PMBus interface, 0.6–3.63-V output, and digital loop compensation - no remote sense pins | Requires MCU-based configuration and telemetry; no differential sensing for load-point accuracy | Choose for systems needing real-time telemetry, margining, or dynamic voltage scaling; not suitable for analog-only or remote-sense-critical designs |
Compared with TPS548B27RYLR, TPS548B22RMLR offers identical layout and control but reduced current capability and protection behavior, while MP2964GQKT-Z trades analog simplicity and remote sensing for digital configurability and telemetry - neither is pin-compatible, and both require PCB redesign for replacement.
Availability
TPS548B27RYLR is available at Aetrix Electronics and suitable for rack server, data center switch, and industrial PC applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.
Supply support for TPS548B27RYLR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-efficiency power management ICs for computing infrastructure.
The TPS548B27RYLR belongs to TI's D-CAP3™ synchronous buck converter product line, designed specifically for high-current, low-voltage point-of-load regulation in space-constrained data center and enterprise computing systems.
FAQ
What is the minimum input voltage required for TPS548B27RYLR to deliver 20-A output?
The TPS548B27RYLR requires a minimum 2.7 V input to sustain 20-A output when an external 3.13–3.6 V bias is applied to the VCC pin. With only the internal 3-V LDO active, the minimum valid input rises to 4.0 V - verified across –40°C to +125°C junction temperature per Section 6.3 of the datasheet. Below these thresholds, current capability degrades progressively.
How does the TPS548B27RYLR implement remote voltage sensing?
The TPS548B27RYLR uses dedicated VSNS+ and VSNS– pins to close the feedback loop at the load rather than at the converter output. VSNS– connects to the load ground reference, and VSNS+ connects to the load's positive rail. This differential measurement cancels PCB trace resistance effects, enabling ±1% output regulation accuracy at the point of load - confirmed by test data in Figure 6-7 and Section 7.3.4.
Can TPS548B27RYLR operate without external compensation components?
Yes. The TPS548B27RYLR's D-CAP3™ control architecture eliminates the need for external compensation networks. Its adaptive on-time modulation with emulated current sensing ensures stability with all ceramic output capacitors - a design feature explicitly validated in Section 7.1 and Figure 7-2 of the datasheet, reducing BOM count and layout complexity.
What thermal derating applies to TPS548B27RYLR at 70°C ambient?
At 70°C ambient with 400 LFM airflow and standard 2-layer PCB layout, the TPS548B27RYLR sustains full 20-A output without derating - per Safe Operating Area curves in Figures 6-3 and 6-5. Junction temperature remains below 125°C due to RθJB = 9.2°C/W; above 70°C ambient, output current must be reduced linearly per thermal limits in Section 6.4.
Does TPS548B27RYLR support prebiased start-up, and how is it enabled?
Yes. TPS548B27RYLR supports prebiased start-up natively - no external components required. When EN is asserted while the output is already charged, the device prevents reverse current flow by disabling the low-side FET until the soft-start ramp reaches the programmed output voltage. This behavior is documented in Figure 6-15 and Section 7.3.2.
TPS548B27RYLR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 19-PowerTFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.7V
- Voltage - Input (Max):
- 16V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 20A
- Frequency - Switching:
- 600kHz, 800kHz, 1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 19-VQFN-FCRLF (4x3)
TPS548B27RYLR FAQ
1.How can I place an order for TPS548B27RYLR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS548B27RYLR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS548B27RYLR reliable?
The price and inventory of TPS548B27RYLR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS548B27RYLR is usually 5 days.
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TPS548B27RYLR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS548B27RYLR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS548B27RYLR?
For technical support, including TPS548B27RYLR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS548B27RYLR requirements.
6.How does Aetrix verify that TPS548B27RYLR is sourced from the original manufacturer or authorized distributors?
All TPS548B27RYLR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS548B27RYLR meets industry standards.
7.What is the process for return or replacement of TPS548B27RYLR?
All TPS548B27RYLR units undergo pre-shipment inspection (PSI). If there is an issue with TPS548B27RYLR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS548B27RYLR part is unused and in its original packaging.
Return procedure for TPS548B27RYLR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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