Texas Instruments TPS54917RUVR
- Part No.:
- TPS54917RUVR
- Manufacturer:
- Texas Instruments
- Package:
- 34-VFQFN Exposed Pad
- Datasheet:
-
TPS54917RUVR.pdf
- Description:
- IC REG BUCK ADJ 9A 34VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,001
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS54917 from Texas Instruments is a 3-V to 4-V input, 9-A synchronous buck DC-DC converter with integrated 13-mΩ high-side and low-side MOSFETs, adjustable output down to 0.9 V (±1% accuracy), and externally compensated voltage-mode control-designed for point-of-load regulation in FPGA and ASIC power delivery.
For engineers reviewing the TPS54917 datasheet, TPS54917 pinout, TPS54917 application, or TPS54917 equivalent, key selection considerations include its 34-pin VQFN (RUV) thermal package, 280 kHz–1.6 MHz programmable switching frequency, cycle-by-cycle current limiting, thermal shutdown at 150°C, and PWRGD open-drain power-good signaling for supply sequencing.
Technical Context
The TPS54917 implements voltage-mode PWM control with a high-performance error amplifier supporting external Type-3 compensation, enabling stable operation with ceramic or electrolytic output capacitors. Its adaptive dead-time logic prevents shoot-through by coordinating high-side and low-side gate drive timing based on real-time PH node voltage thresholds.
Switching frequency is selectable via SYNC pin state (350 kHz or 550 kHz fixed) or RT resistor (280 kHz–1.6 MHz), and synchronization to external clocks up to 1.6 MHz is supported. Undervoltage lockout (2.95 V start / 2.8 V stop) and internal 3.35-ms slow-start ensure controlled power-up under varying input conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3 V to 4 V - supports direct regulation from 3.3-V distributed bus without pre-regulation. |
| Continuous Output Current | 9 A - delivered via integrated 13-mΩ (typ.) MOSFETs, enabling compact high-current POL solutions. |
| Output Voltage Accuracy | ±1% over line/load/temperature - ensures tight regulation for core voltages of FPGAs and DSPs. |
| Switching Frequency Range | 280 kHz to 1.6 MHz - allows optimization of inductor size, efficiency, and EMI profile per design constraints. |
| Thermal Shutdown Threshold | 150°C (trip), 140°C (hysteresis) - protects against sustained overload or poor heatsinking in enclosed systems. |
| Power-Good Output | Open-drain PWRGD with 90% VREF threshold - provides reliable reset signaling and supply sequencing capability. |
| UVLO Threshold | 2.95 V start / 2.8 V stop with 160 mV hysteresis - prevents erratic startup during brownout conditions. |
Pinout & Package
TPS54917 is housed in a thermally enhanced 34-pin VQFN (RUV) package measuring 3.5 mm × 7.0 mm with an exposed PowerPAD™ thermal pad soldered to AGND for efficient heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pins 21–25) | Input power supply | High-current input for MOSFET switches and internal bias regulator; requires local 10-µF ceramic bypass to PGND. |
| PH (Pins 6–12) | Phase node | Junction of internal high-side/low-side FETs; connects directly to output inductor and must be routed with minimal loop area. |
| PGND (Pins 13–20, 30–34) | Power ground return | High-current return path for low-side FET and input/output capacitors; requires wide copper pour and single-point tie to AGND. |
| AGND (Pin 1) | Analog reference ground | Reference for COMP, VSENSE, SS/ENA, RT, SYNC, and VBIAS; connected to PowerPAD via dedicated trace. |
| VSENSE (Pin 2) | Error amplifier inverting input | Monitors regulated output via external resistor divider; sets feedback gain and stability margins. |
| COMP (Pin 3) | Error amplifier output | Drives external Type-3 compensation network between COMP and VSENSE to stabilize loop response. |
| PWRGD (Pin 4) | Power-good status | Open-drain output asserted high when VSENSE ≥ 90% VREF; used for processor reset or downstream enable sequencing. |
| BOOT (Pin 5) | Bootstrap supply | Drives high-side FET gate via 0.022–0.1 µF ceramic capacitor to PH; critical for maintaining gate drive above VIN. |
| SS/ENA (Pin 27) | Enable/slow-start control | Logic-enable input (1.2 V threshold) and external capacitor interface for adjustable soft-start time. |
| SYNC (Pin 28) | Frequency synchronization | Accepts external clock (330–1600 kHz) or selects internal 350/550 kHz modes; requires RT resistor when synchronizing. |
| RT (Pin 29) | Frequency setting | Resistor-to-AGND sets free-running frequency (280 kHz–1.6 MHz); value determines oscillator ramp slope. |
| VBIAS (Pin 26) | Bias regulator output | 2.7–2.9 V internal LDO output; powers internal circuitry and may serve as clean analog reference for external circuits. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 13-mΩ MOSFETs | Enables >90% peak efficiency at 9 A while eliminating external switch selection and layout complexity. |
| Externally compensated voltage-mode control | Supports full flexibility in output filter design-including mixed ceramic/electrolytic capacitors-and enables precise transient response tuning. |
| Programmable 280 kHz–1.6 MHz switching | Allows trade-off between inductor size (higher fSW → smaller L) and conduction losses (lower fSW → higher efficiency at light load). |
| Adaptive dead-time control | Prevents shoot-through by dynamically delaying high-side turn-on until low-side gate falls below 2 V, and vice versa. |
| Robust protection suite | Includes cycle-by-cycle current limit (11–15 A trip), thermal shutdown (150°C), UVLO, and PWRGD fault signaling. |
Applications
| FPGA Core Power Supply | ASIC I/O Voltage Regulation |
|---|---|
Use Scenario: Delivering tightly regulated 0.85–1.2 V at up to 9 A to Xilinx or Intel FPGA core rails with fast load transients. IC Role / Device Role / Timing Role: Primary synchronous buck regulator providing dynamic point-of-load conversion with PWRGD sequencing control. Use Value: ±1% output accuracy and high-bandwidth error amplifier maintain voltage within FPGA core spec limits during 5-A/µs load steps. |
Use Scenario: Generating 1.8 V or 2.5 V I/O supply for multi-million-gate ASICs in telecom line cards with strict ripple and noise requirements. IC Role / Device Role / Timing Role: High-current DC-DC converter with externally compensated loop for optimal phase margin and EMI filtering. Use Value: 34-pin VQFN package and 1.6 MHz max switching enable small footprint and low-profile inductors meeting <10 mVpp ripple targets. |
| Optical Transceiver Module | Industrial DSP Power Rail |
Use Scenario: Powering 3.3-V analog front-end and digital signal processors inside SFP+ and QSFP modules with limited board space. IC Role / Device Role / Timing Role: Compact, thermally optimized buck converter operating from backplane 3.3-V supply with synchronized switching to reduce system EMI. Use Value: SYNC pin enables alignment with system clock domain, minimizing beat frequencies and easing EMC certification. |
Use Scenario: Supplying 1.2 V to TI C6000 or Analog Devices SHARC DSPs in ruggedized industrial controllers requiring long-term reliability. IC Role / Device Role / Timing Role: Protected POL regulator with thermal shutdown, UVLO, and current limiting for unattended operation in harsh environments. Use Value: 125°C max junction rating and robust 15-A current limit ensure continuous operation under sustained overload or ambient temperature spikes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54910RHLT | Larger 40-pin VQFN (4.5 × 6 mm); fixed 350 kHz or 550 kHz only; 15-mΩ MOSFETs; lower max output current (8 A). | Requires more PCB area; less flexible frequency tuning; slightly lower efficiency at 9 A due to higher RDS(on). | Choose when legacy layout compatibility or lower cost outweighs need for 1.6-MHz operation and 9-A capability. |
| MP2964GQKT-Z | Monolithic 9-A buck with 3–18 V input; 500 kHz fixed; integrated telemetry; no RT/SYNC pins; different pinout and compensation scheme. | Not pin-compatible; lacks external frequency programming or synchronization; designed for server VR13/IMVP8 compliance. | Consider only for new designs where telemetry, wider VIN, or IMVP8 features are required-and full redesign is acceptable. |
Compared with TPS54917, TPS54910RHLT offers proven reliability but sacrifices frequency flexibility and thermal performance in compact layouts, while MP2964GQKT-Z provides telemetry and broader input range at the cost of pin-incompatibility and loss of external loop control.
Availability
TPS54917 is available at Aetrix Electronics and suitable for FPGA core supplies, ASIC I/O regulation, optical transceiver modules, and industrial DSP power rails requiring stable component supply, long-lifecycle support, and consistent parametric performance across production batches.
Supply support for TPS54917 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC-DC conversion and automotive-grade reliability.
The TPS54917 belongs to TI's SWIFT™ family of high-current synchronous buck regulators, engineered specifically for space-constrained, high-density point-of-load applications in networking, computing, and communications infrastructure.
FAQ
What is the maximum recommended output current for the TPS54917?
The TPS54917 is rated for continuous 9-A output current under recommended operating conditions (TJ ≤ 125°C, VI = 3–4 V). Its integrated 13-mΩ MOSFETs and 34-pin VQFN PowerPAD™ package enable this rating with proper PCB thermal design-specifically, ≥4 cm² of 2-oz copper connected to the thermal pad. Peak current limit is 11–15 A, but sustained operation above 9 A requires derating based on ambient temperature and airflow.
Does the TPS54917 support external frequency synchronization?
Yes, the TPS54917 supports external synchronization via the SYNC pin across a 330 kHz to 1.6 MHz range. To synchronize, apply a clean square-wave clock to SYNC and connect an RT resistor to AGND-selected to set the free-running frequency to ~80% of the external clock frequency. This feature reduces system-level EMI by aligning switching edges with other converters or clocks in the same enclosure.
How is the output voltage set on the TPS54917?
The TPS54917 uses resistive feedback from the output to the VSENSE pin (Pin 2) to set output voltage. The internal 0.891-V reference is compared against the divided output, so VO = 0.891 × (1 + R1/R2), where R1 connects VO to VSENSE and R2 connects VSENSE to AGND. Accuracy is ±1% over line, load, and temperature-verified by TI's production test across the full operating range of the TPS54917.
What protection features does the TPS54917 include?
The TPS54917 integrates cycle-by-cycle overcurrent protection (11–15 A trip), thermal shutdown (150°C trip, 140°C release), undervoltage lockout (2.95 V start), and open-drain PWRGD signaling. It also includes leading-edge blanking (100 ns) to prevent false current-limit triggering and adaptive dead-time control to eliminate shoot-through. These protections operate autonomously without external components, ensuring robust operation in demanding environments.
Can the TPS54917 be used with ceramic output capacitors only?
Yes, the TPS54917 supports ceramic-only output capacitors thanks to its externally compensated voltage-mode architecture and high-performance error amplifier. Type-3 compensation networks (typically R-C-R-C configurations) allow stable loop response with low-ESR ceramics, eliminating the need for bulk electrolytic capacitors. This reduces solution size, improves reliability, and enhances transient response-key advantages confirmed in TI's TPS54917 evaluation module test reports.
TPS54917RUVR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™
- Package/Case:
- 34-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 3V
- Voltage - Input (Max):
- 4V
- Voltage - Output (Min/Fixed):
- 0.891V
- Voltage - Output (Max):
- 3.6V
- Current - Output:
- 9A
- Frequency - Switching:
- 350kHz, 550kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 34-VQFN (7x3.5)
TPS54917RUVR FAQ
1.How can I place an order for TPS54917RUVR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54917RUVR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54917RUVR reliable?
The price and inventory of TPS54917RUVR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54917RUVR is usually 5 days.
3.What payment methods are accepted for TPS54917RUVR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54917RUVR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS54917RUVR?
TPS54917RUVR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS54917RUVR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54917RUVR?
For technical support, including TPS54917RUVR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54917RUVR requirements.
6.How does Aetrix verify that TPS54917RUVR is sourced from the original manufacturer or authorized distributors?
All TPS54917RUVR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54917RUVR meets industry standards.
7.What is the process for return or replacement of TPS54917RUVR?
All TPS54917RUVR units undergo pre-shipment inspection (PSI). If there is an issue with TPS54917RUVR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54917RUVR part is unused and in its original packaging.
Return procedure for TPS54917RUVR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS54917RUVR Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

