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Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Special Purpose Regulators

Texas Instruments TPS54972PWPRG4

Name: TPS54972PWPRG4
Brand: Texas Instruments
SKU: TPS54972PWPRG4
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: TPS54972PWPRG4

Manufacturer:: Texas Instruments

Category:: Special Purpose Regulators

Package:: 28-PowerTSSOP (0.173", 4.40mm Width)

Datasheet:: TPS54972PWPRG4.pdf

Description:: IC REG CONV DDR 1OUT 28HTSSOP

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Product details

Overview

TPS54972PWPRG4 from Texas Instruments is a 9-A synchronous buck PWM converter with integrated high- and low-side MOSFETs, designed for DDR memory termination and active GTL/SSTL logic family termination. It operates from 3.0 V to 4.0 V input, delivers 1.25 V output at up to 9 A continuous source/sink, and features adjustable switching frequency (280–700 kHz) and external reference tracking (0.2–1.75 V).

For engineers reviewing the TPS54972PWPRG4 datasheet, TPS54972PWPRG4 pinout, TPS54972PWPRG4 application, or TPS54972PWPRG4 equivalent, this device is selected for precision point-of-load regulation in high-speed digital systems requiring fast transient response, tight load/line regulation (<0.04%/V, <0.03%/A), and thermal robustness via PowerPAD™ package.

Technical Context

The TPS54972PWPRG4 implements a voltage-mode synchronous buck architecture with an internal high-performance error amplifier (90–110 dB open-loop gain, 3–5 MHz unity-gain bandwidth) and adaptive dead-time control to prevent shoot-through. Its PWM comparator uses a 1-V peak-to-peak ramp with 0.75-V valley and supports minimum on-time of 200 ns.

It integrates dual N-channel MOSFETs with matched r_DS(on) (14–30 mΩ at V_IN = 3.0–3.6 V), a dedicated VBIAS LDO (2.70–2.90 V, 100 mA), and independent AGND/PGND planes to isolate noise-sensitive analog circuitry from high-current power paths.

Key Specifications

Parameter	Value and Actual Design Meaning
Output current	9 A continuous source/sink - enables full DDR termination compliance and active GTL/SSTL bus driving without external current boost.
Input voltage range	3.0 V to 4.0 V - matches standard DDR VDDQ rails and eliminates need for pre-regulation in 3.3-V systems.
Switching frequency	Fixed 350 kHz or adjustable 280–700 kHz - allows optimization of inductor size, efficiency, and EMI profile per layout constraints.
Output voltage accuracy	±1% over temperature - ensures stable termination voltage under varying junction conditions (–40°C to 125°C).
r_DS(on) (high/low-side)	14–30 mΩ - minimizes conduction loss and thermal rise at 9-A load, supporting >90% efficiency at 3.3-V input / 1.25-V output.
Tracking range	6% to 90% of V_IN - supports precise VTT = ½ × VDDQ tracking across process/voltage/temperature corners.
Quiescent current	11–23.5 mA - balances light-load efficiency with fast wake-up capability during dynamic DDR bus activity.

Pinout & Package

TPS54972PWPRG4 is housed in a thermally enhanced 28-pin HTSSOP (PWP) PowerPAD™ package measuring 6.4 mm × 9.7 mm, with an exposed thermal pad soldered to AGND for low-junction-to-ambient thermal resistance (14.4°C/W with proper PCB layout).

Pin/Terminal	Circuit Role	Design Meaning
AGND (Pin 1)	Analog ground reference	Return for compensation network, REFIN, RT, VBIAS capacitor, and SYNC - must be isolated from PGND except at single-point connection to minimize noise coupling.
VSENSE (Pin 2)	Error amplifier inverting input	Connects to output voltage divider - sets regulation point and enables precise tracking of external reference (e.g., VDDQ/2).
COMP (Pin 3)	Error amplifier output	Drives external Type II/III compensation network - determines loop stability, bandwidth (~70–80 kHz crossover), and transient response.
STATUS (Pin 4)	Open-drain power-good indicator	Asserts low if VIN < UVLO (2.95 V), VBIAS not settled, or thermal shutdown active - used for system sequencing and fault monitoring.
BOOT (Pin 5)	Bootstrap supply for high-side gate driver	Requires 0.022–0.1 µF low-ESR ceramic capacitor to PH - enables efficient high-side FET drive without external charge pump.
PH (Pins 6–14)	Phase node (switching output)	High-current connection to output inductor - multiple pins reduce trace inductance and resistive loss at 9-A peak currents.
RT (Pin 28)	Oscillator frequency setting	Resistor to AGND selects frequency: 68 kΩ → 700 kHz, 100 kΩ → 500 kHz, 180 kΩ → 280 kHz, or floating → 350 kHz.
REFIN (Pin 26)	External tracking reference input	High-impedance input (0.2–1.75 V range) - accepts DAC-controlled or buffered VDDQ/2 signal for dynamic termination voltage adjustment.
VBIAS (Pin 25)	Internal bias regulator output	Supplies 2.70–2.90 V to internal circuits - requires 0.1–1.0 µF ceramic bypass to AGND; can power external low-noise analog circuitry.
VIN (Pins 20–24)	Main input supply	Accepts 3.0–4.0 V; multiple pins reduce IR drop and enable parallel 10-µF ceramic bypassing close to PGND.
PGND (Pins 15–19)	Power ground return	High-current return for low-side FET and input/output capacitors - must connect to large copper areas and avoid shared traces with AGND.
ENA (Pin 27)	Enable control input	Logic-high (>1.20 V) enables operation; logic-low (<0.82 V) disables with <1.4 mA quiescent current - supports system-level power sequencing.

Key Features

Feature	Design Value
Integrated 14–30 mΩ MOSFETs	Eliminates external FETs and gate drivers, reducing BOM count and PCB area while maintaining >90% efficiency at full load.
Adjustable 280–700 kHz switching	Enables trade-off between inductor size (smaller at higher f_SW) and conduction vs. switching loss - optimized via single RT resistor.
0.2–1.75 V external reference tracking	Supports dynamic VTT adjustment in DDR systems where VDDQ varies, ensuring termination remains precisely at half-rail.
Thermal shutdown (135–165°C) + peak current limit (11–15 A)	Protects against sustained overload and board-level thermal runaway without external sensing components.
Separate AGND/PGND planes	Prevents noise from high di/dt power loops from degrading error amplifier performance and output voltage accuracy.

Applications

DDR Memory Termination Voltage	Active GTL/SSTL Logic Termination
Use Scenario: Providing precise VTT = ½ × VDDQ termination for DDR2/DDR3 memory buses operating at 3.3 V or 2.5 V VDDQ. IC Role / Device Role / Timing Role: Synchronous buck regulator sourcing/sinking up to ±9 A to maintain stable termination voltage during rapid bus transitions. Use Value: Ensures signal integrity by eliminating reflections and ground bounce, meeting JEDEC DDR timing margins under worst-case load transients.	Use Scenario: Driving termination for high-speed GTL+ and SSTL_18 logic families in networking ASICs and FPGA I/O banks. IC Role / Device Role / Timing Role: Precision point-of-load regulator delivering 1.25 V at 9 A with sub-50-mV output ripple and <2.5-µs transient recovery. Use Value: Maintains logic threshold stability across temperature and supply variation, enabling reliable 200+ MHz bus operation.
DAC-Controlled High-Current Output Stage	Precision Point-of-Load Power Supply
Use Scenario: Generating programmable termination voltage in test equipment using DAC output as REFIN signal. IC Role / Device Role / Timing Role: Tracking regulator interpreting DAC voltage (0.2–1.75 V) as setpoint - supports real-time VTT adjustment during characterization. Use Value: Enables automated margin testing and adaptive voltage scaling without hardware changes or additional regulators.	Use Scenario: Delivering tightly regulated 1.25 V to noise-sensitive analog front-ends or high-precision ADC/DAC reference domains. IC Role / Device Role / Timing Role: Low-noise buck converter with 0.03%/A load regulation and separate AGND/PGND isolation minimizing PSRR degradation. Use Value: Reduces output voltage drift under dynamic load steps, preserving 16-bit+ data converter accuracy in mixed-signal systems.

DDR Memory Termination Voltage

Active GTL/SSTL Logic Termination

Use Scenario: Providing precise VTT = ½ × VDDQ termination for DDR2/DDR3 memory buses operating at 3.3 V or 2.5 V VDDQ.

IC Role / Device Role / Timing Role: Synchronous buck regulator sourcing/sinking up to ±9 A to maintain stable termination voltage during rapid bus transitions.

Use Value: Ensures signal integrity by eliminating reflections and ground bounce, meeting JEDEC DDR timing margins under worst-case load transients.

Use Scenario: Driving termination for high-speed GTL+ and SSTL_18 logic families in networking ASICs and FPGA I/O banks.

IC Role / Device Role / Timing Role: Precision point-of-load regulator delivering 1.25 V at 9 A with sub-50-mV output ripple and <2.5-µs transient recovery.

Use Value: Maintains logic threshold stability across temperature and supply variation, enabling reliable 200+ MHz bus operation.

DAC-Controlled High-Current Output Stage

Precision Point-of-Load Power Supply

Use Scenario: Generating programmable termination voltage in test equipment using DAC output as REFIN signal.

IC Role / Device Role / Timing Role: Tracking regulator interpreting DAC voltage (0.2–1.75 V) as setpoint - supports real-time VTT adjustment during characterization.

Use Value: Enables automated margin testing and adaptive voltage scaling without hardware changes or additional regulators.

Use Scenario: Delivering tightly regulated 1.25 V to noise-sensitive analog front-ends or high-precision ADC/DAC reference domains.

IC Role / Device Role / Timing Role: Low-noise buck converter with 0.03%/A load regulation and separate AGND/PGND isolation minimizing PSRR degradation.

Use Value: Reduces output voltage drift under dynamic load steps, preserving 16-bit+ data converter accuracy in mixed-signal systems.

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck regulator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS54672PWP	6-A output rating, identical pinout and feature set except lower current capability and 12–24 mΩ r_DS(on).	Suitable for DDR1/DDR2 systems with ≤6 A termination demand; cannot support full 9-A DDR3 VTT loads.	Select when design margin allows reduced current headroom and cost sensitivity outweighs future-proofing.
TPS54872PWP	8-A output, same package and control architecture but optimized for lower quiescent current (8–15 mA) and tighter UVLO (2.98 V start).	Better suited for battery-backed or low-power DDR applications where standby efficiency and cold-start reliability are critical.	Choose for portable or energy-constrained systems needing extended low-I_Q operation without sacrificing 8-A peak capability.

Compared with TPS54672PWP and TPS54872PWP, the TPS54972PWPRG4 provides the highest continuous current (9 A), widest tracking range (6–90% V_IN), and most robust thermal performance - making it the only option qualified for full-spec DDR3 VTT and high-density SSTL bus termination.

Availability

TPS54972PWPRG4 is available at Aetrix Electronics and suitable for DDR memory subsystems, high-speed logic termination, and precision point-of-load power supplies requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for TPS54972PWPRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion and power integrity solutions.

The TPS54972PWPRG4 belongs to TI's SWIFT™ family of synchronous buck regulators, engineered specifically for high-current, low-voltage tracking applications in DDR memory and high-speed digital logic interfaces.

FAQ

What is the maximum continuous output current supported by the TPS54972PWPRG4?

The TPS54972PWPRG4 supports 9 A continuous output current in both sourcing and sinking modes. This rating is validated under recommended PCB layout conditions with the PowerPAD™ thermally connected to AGND using ≥8 thermal vias and a 3-inch × 3-inch 1-oz copper plane. At 125°C junction temperature and 700 kHz switching, derating applies per the dissipation ratings table - full 9-A operation requires adequate airflow or heatsinking.

Does the TPS54972PWPRG4 require external MOSFETs or gate drivers?

No, the TPS54972PWPRG4 integrates both high-side and low-side N-channel MOSFETs with typical r_DS(on) of 14–30 mΩ. It also includes fully integrated gate drivers, bootstrap circuitry (with internal 2.5-Ω switch), adaptive dead-time control, and internal compensation for the error amplifier - eliminating all external power-stage components.

How does the TPS54972PWPRG4 achieve precise DDR termination voltage tracking?

The TPS54972PWPRG4 achieves precise DDR termination via its REFIN pin, which accepts an externally supplied reference (e.g., buffered VDDQ/2). The device tracks this input from 0.2 V to 1.75 V with 6–90% V_IN range, and its high-gain error amplifier (90–110 dB) ensures <±1% output accuracy over temperature and load - critical for meeting DDR2/DDR3 VTT tolerance specs.

What thermal management is required for the TPS54972PWPRG4 at full 9-A load?

At full 9-A load, the TPS54972PWPRG4 requires the PowerPAD™ to be soldered to a minimum 5 mm × 5 mm exposed copper area connected to AGND via ≥8 × 0.013″ vias. A 3-inch × 3-inch internal 1-oz ground plane is recommended. With proper layout, thermal impedance drops to 14.4°C/W, allowing 6.94 W dissipation at 25°C ambient - sufficient for 9-A operation at 3.3-V input and 1.25-V output.

Can the TPS54972PWPRG4 operate with input voltages below 3.0 V?

No - the TPS54972PWPRG4 has a hard UVLO threshold of 2.95 V (typical start) and 2.80 V (stop), with hysteresis of 0.16 V. Operation below 3.0 V violates recommended operating conditions and will cause intermittent shutdown. The absolute maximum rating for VIN is 4.5 V, and the device is specified only for 3.0–4.0 V input per datasheet Section 6.3.

TPS54972PWPRG4 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: SWIFT™

Package/Case:: 28-PowerTSSOP (0.173", 4.40mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Discontinued at Digi-Key

Applications:: Converter, DDR

Voltage - Input:: 4V ~ 6V

Number of Outputs:: 1

Voltage - Output:: 0.2V ~ 3.3V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 28-HTSSOP

TPS54972PWPRG4 FAQ

1.How can I place an order for TPS54972PWPRG4 through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS54972PWPRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS54972PWPRG4 reliable?

The price and inventory of TPS54972PWPRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54972PWPRG4 is usually 5 days.

3.What payment methods are accepted for TPS54972PWPRG4?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS54972PWPRG4 transactions.

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4.How is shipping managed for TPS54972PWPRG4?

TPS54972PWPRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS54972PWPRG4 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS54972PWPRG4?

For technical support, including TPS54972PWPRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54972PWPRG4 requirements.

6.How does Aetrix verify that TPS54972PWPRG4 is sourced from the original manufacturer or authorized distributors?

All TPS54972PWPRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54972PWPRG4 meets industry standards.

7.What is the process for return or replacement of TPS54972PWPRG4?

All TPS54972PWPRG4 units undergo pre-shipment inspection (PSI). If there is an issue with TPS54972PWPRG4, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS54972PWPRG4 part is unused and in its original packaging.

Return procedure for TPS54972PWPRG4:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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