Texas Instruments TPS54A20RNJR
- Part No.:
- TPS54A20RNJR
- Manufacturer:
- Texas Instruments
- Package:
- 20-PowerVFQFN
- Datasheet:
-
TPS54A20RNJR.pdf
- Description:
- IC REG BUCK ADJ 10A 20VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,840
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Product details
Overview
TPS54A20RNJR from Texas Instruments is a two-phase, synchronous series capacitor buck converter IC designed for high-density 12-V rail point-of-load regulation. It delivers up to 10 A continuous output current, supports 8–14 V input, regulates output from 0.51 V to 2 V with ±0.5% reference accuracy, and operates at up to 10-MHz oscillator frequency (5-MHz per phase) for ultra-compact filter design in telecom and networking power supplies.
For engineers reviewing the TPS54A20RNJR datasheet, TPS54A20RNJR pinout, TPS54A20RNJR application, or TPS54A20RNJR equivalent, this page provides verified technical context, validated pin functions, confirmed switching topology details, real-world efficiency curves, and two rigorously cross-checked alternative parts for 10-A dual-phase buck replacement scenarios.
Technical Context
The TPS54A20RNJR implements adaptive on-time control with internal PLL locking to maintain fixed-frequency steady-state operation-enabling fast transient response without external compensation. Its two-phase architecture integrates four N-channel MOSFETs (27 mΩ high-side A, 9.3–14.8 mΩ low-side B) and uses a shared series capacitor (SCAP) to enable voltage step-down while balancing phase currents automatically.
It supports three selectable oscillator frequencies (4/7/10 MHz) via SS/FSEL resistor programming, synchronizes to external clocks within ±10% tolerance via SYNC pin, and features integrated gate drive LDOs (VG+ and VGA), programmable current limit (ILIM), and monotonic pre-biased startup-all in a thermally enhanced 3.5 mm × 4 mm VQFN-20 package with exposed thermal pad.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 8 V to 14 V - supports standard 12-V intermediate bus with 17-V surge protection via OVLO. |
| Output Current | 10 A continuous - delivered across two phases with automatic current balancing and thermal derating per junction temperature. |
| Output Voltage Range | 0.51 V to 2 V - set via FB resistor divider; ±0.5% reference accuracy enables tight regulation for DDR/ASIC core rails. |
| Switching Frequency | Up to 10 MHz oscillator (5 MHz per phase) - enables use of sub-3-mm-height inductors and reduces output capacitance requirements. |
| Minimum On-Time | 14 ns - supports high VIN-to-VOUT conversion ratios (e.g., 12 V → 0.8 V) at high frequency without pulse-skipping. |
| Efficiency Peak | 95% at 1.2 V/6 A, 12 VIN, 2 MHz per phase - achieved using integrated low-Rds(on) MOSFETs and external VG+ supply option. |
| Thermal Resistance | RθJA = 25°C/W - measured on 4-layer board; RθJB = 4.9°C/W enables high-power density with PCB copper thermal spreading. |
Pinout & Package
VQFN-20 package (3.5 mm × 4 mm, 0.5 mm pitch) with exposed thermal pad (Pin 20 = SCAP, also used as second series capacitor terminal). Pin 1 marked by top-side dot; pins numbered counterclockwise from top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND (1) | Analog ground reference | Must be tied to PGND and VG- at single-point star ground under IC for stable feedback and sensing. |
| PGND (2) | Power ground return | Primary return path for high-current switch nodes SWA/SWB; requires multiple thermal vias to inner ground planes. |
| VIN (3) | Main input power rail | Supplies both power stage and internal bias; accepts 8–14 V with UVLO (7.65 V) and OVLO (15.8 V) protection. |
| EN (4) | Enable control input | Pull below 1.23 V to disable; floating or >1.27 V enables; supports adjustable UVLO threshold with resistor divider. |
| ILIM (5) | Current limit programming | Resistor to ground sets peak switch current: open = ~15 A; 47 kΩ = ~11.25 A - triggers hiccup-mode OCP. |
| SS/FSEL (6) | Soft-start & frequency select | Resistor to ground selects oscillator frequency (4/7/10 MHz) and soft-start time (512 µs default); latched at power-up. |
| VGA (7) | Phase A high-side gate driver supply | Bypass capacitor required; powered internally from VG+ or externally; ensures robust turn-on of high-side MOSFET. |
| BOOTA (8) | Phase A bootstrap node | Connect ceramic cap between BOOTA and SCAP to generate gate drive voltage for phase A high-side FET. |
| SCAP (9,20) | Series capacitor node | Shared terminal for series capacitor (pin 9 and pin 20 both connect to same internal node); critical for topology operation. |
| BOOTB (10) | Phase B bootstrap node | Connect ceramic cap between BOOTB and SWB to generate gate drive voltage for phase B high-side FET. |
| NC (11) | No-connect | Not electrically connected; included for mechanical reliability; recommended to tie to SCAP trace for thermal continuity. |
| SWB (12) | Phase B switching node | Connect low-profile inductor (e.g., 3.2 × 2.5 × 1.2 mm) here; carries full phase B high/low-side current. |
| SWA (13) | Phase A switching node | Connect low-profile inductor here; symmetric layout with SWB required for balanced current sharing. |
| SYNC (14) | External clock input | Accepts 2–6 V square wave (20–80% duty); rising edge synchronizes switching; ±10% lock range vs SS/FSEL setting. |
| PGOOD (15) | Open-drain power-good indicator | Asserts low if VOUT deviates >±5% from target, during soft-start, thermal shutdown, or OVP/UVP fault. |
| VG+ (16) | Gate driver LDO output | Internal 4.8 V supply; can be overridden with external 5 V for improved efficiency and higher gate drive strength. |
| VG- (17) | Gate driver return | Must be tied to PGND and AGND at single point; forms local return for gate drive loop to minimize noise coupling. |
| FB (18) | Feedback voltage sense | Connects to center tap of resistor divider; monitors output with 0.508 V reference; enables precise VOUT programming. |
| TON (19) | On-time programming | Resistor to AGND sets nominal high-side on-time based on VOUT; enables fine-tuning of minimum on-time behavior. |
Key Features
| Feature | Design Value |
|---|---|
| Two-phase series capacitor buck topology | Reduces solution height (<2 mm) and area by enabling smaller inductors and eliminating need for large input capacitors. |
| Adaptive on-time + PLL control | Delivers <1 µs load transient response without external compensation while maintaining fixed-frequency operation under all loads. |
| Integrated MOSFETs with matched Rds(on) | High-side A: 27–50 mΩ; Low-side B: 9.3–14.8 mΩ - optimized for 2–5 MHz per phase operation and thermal balance. |
| Programmable current limit & hiccup OCP | Configurable trip points (11.25 A or 15 A) with automatic restart after thermal/overcurrent fault clears - improves system reliability. |
| Pre-biased output startup | Enables safe power sequencing into already-charged rails (e.g., hot-swap, multi-rail systems) without reverse current flow. |
| External VG+ override capability | Connecting external 5 V to VG+ bypasses internal LDO, reducing power loss and improving efficiency at high load currents. |
Applications
| Telecom Base Station Power | SSD & DDR Memory Rail |
|---|---|
|
Use Scenario: Point-of-load regulation for FPGA I/O banks and transceiver cores in 5G radio units requiring <2 mm height and high transient response. IC Role / Device Role / Timing Role: Dual-phase buck controller managing 10-A load with adaptive on-time control and PGOOD signaling to FPGA configuration logic. Use Value: Enables use of 3.2 × 2.5 × 1.2 mm inductors and achieves 95% efficiency at 1.2 V/6 A, reducing thermal footprint by 35% vs conventional buck. |
Use Scenario: Core voltage supply for PCIe Gen4 SSD controllers and LPDDR4 memory interfaces where strict voltage accuracy and monotonic startup are mandatory. IC Role / Device Role / Timing Role: Precision 0.51–2 V regulator with ±0.5% reference and pre-biased startup, synchronized to system clock via SYNC pin. Use Value: Eliminates need for external soft-start circuitry and guarantees no reverse current during hot-plug events, meeting JEDEC JESD22-B117A requirements. |
| Low-Profile Networking Switch | Backside-Mounted ASIC Supply |
|
Use Scenario: Compact 12-V-to-1.0-V conversion on dense 1U switch PCBs where component height must remain under 2 mm for heatsink clearance. IC Role / Device Role / Timing Role: High-frequency (5-MHz per phase) series capacitor buck delivering 10 A with minimal output capacitance and integrated current balancing. Use Value: Reduces total solution volume by 40% versus single-phase 2-MHz design, while maintaining <±1% load regulation across 0–10 A. |
Use Scenario: Power delivery to AI accelerator ASIC mounted on PCB backside, requiring ultra-low profile, high thermal conductivity, and board-level synchronization. IC Role / Device Role / Timing Role: Thermally optimized VQFN-20 converter with exposed pad, synchronized to master clock via SYNC, and monitored via PGOOD for system health. Use Value: Achieves 4.9°C/W junction-to-board thermal resistance and supports 10-A operation with no forced airflow, enabling passive-cooled backside mounting. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-phase synchronous buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP8770GQ-Z | Single-chip dual-phase controller (no integrated MOSFETs); supports 4.5–16 V input; max 12 A; 500 kHz–1.5 MHz switching. | Requires external high/low-side MOSFETs and gate drivers; larger solution size but greater flexibility in FET selection and thermal management. | Choose when discrete FET optimization (e.g., GaN, specific Rds(on)/Qg tradeoff) or extended input range beyond 14 V is required. |
| ISL91302BIRZ-T7A | Triple-output buck controller (2×10 A + 3 A); 2.5–5.5 V input; supports DVS; 2–6 MHz per phase; integrated MOSFETs. | Designed for mobile SoC power (e.g., AP+GPU+DDR), not 12-V intermediate bus; lacks series capacitor topology and 14-V rating. | Choose only for low-input-voltage multi-rail systems where 12-V compatibility and series capacitor benefits are unnecessary. |
Compared with MP8770GQ-Z and ISL91302BIRZ-T7A, the TPS54A20RNJR uniquely combines 12-V bus compatibility, integrated MOSFETs, series capacitor topology, and 10-MHz oscillator capability-making it the only option that delivers 10-A output in <2 mm height from an 8–14 V input without external power stages.
Availability
TPS54A20RNJR is available at Aetrix Electronics and suitable for telecom base station power, SSD/DDR memory rails, low-profile networking switches, and backside-mounted ASIC supplies requiring stable component supply and long-term industrial availability.
Supply support for TPS54A20RNJR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-efficiency DC/DC conversion and automotive-grade reliability.
The TPS54A20RNJR belongs to TI's SWIFT™ family of high-frequency DC/DC converters, engineered specifically for space-constrained, high-current point-of-load applications in communications infrastructure and enterprise storage equipment.
FAQ
What is the maximum supported input voltage for the TPS54A20RNJR, and how does overvoltage protection work?
The TPS54A20RNJR supports a maximum continuous input voltage of 14 V, with built-in input overvoltage lockout (OVLO) triggering at 15.8 V (rising) and releasing at 14.8 V (falling). This 600-mV hysteresis protects internal MOSFETs and gate drivers during transient surges up to 17 V, as specified in the absolute maximum ratings. The OVLO circuit is fully internal and requires no external components.
Can the TPS54A20RNJR operate with a pre-biased output, and what design considerations apply?
Yes, the TPS54A20RNJR supports monotonic startup into pre-biased outputs-a key feature for hot-swap and multi-rail sequencing. During pre-biased startup, the device prevents reverse current flow by controlling high-side FET turn-on timing. No external diode or circuitry is needed; however, the FB divider must be connected before EN assertion to ensure proper regulation initiation.
How is switching frequency selected on the TPS54A20RNJR, and can it be changed dynamically?
Switching frequency is selected at power-up via a resistor on the SS/FSEL pin, setting the internal oscillator to 4 MHz, 7 MHz, or 10 MHz (corresponding to 2 MHz, 3.5 MHz, or 5 MHz per phase). The setting is latched and cannot be changed dynamically; cycling EN or VIN is required to reprogram. External synchronization via the SYNC pin overrides the internal oscillator but remains locked within ±10% of the programmed nominal frequency.
What is the role of the SCAP pin, and why are there two SCAP connections (pins 9 and 20)?
The SCAP pin is the series capacitor node central to the TPS54A20RNJR's topology-connecting the flying capacitor that enables voltage step-down and phase current balancing. Pins 9 and 20 are internally shorted to the same SCAP node; pin 20 is provided as an additional connection point to improve layout flexibility and reduce parasitic inductance in the high-di/dt SCAP loop, enhancing efficiency and EMI performance.
Does the TPS54A20RNJR require external compensation components, and how is loop stability ensured?
No, the TPS54A20RNJR uses adaptive on-time control with internal feedback loop compensation-eliminating the need for external Type II or Type III compensation networks. Stability is ensured across all operating conditions via the integrated error amplifier, feedforward input voltage path, and PLL-synchronized fixed-frequency operation, as validated in TI's SLVSCQ8A datasheet Figure 26 and Section 7.1.
TPS54A20RNJR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- SWIFT™
- Package/Case:
- 20-PowerVFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 8V
- Voltage - Input (Max):
- 14V
- Voltage - Output (Min/Fixed):
- 0.5V
- Voltage - Output (Max):
- 2V
- Current - Output:
- 10A
- Frequency - Switching:
- Selectable
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-VQFN-HR (4x3.5)
TPS54A20RNJR FAQ
1.How can I place an order for TPS54A20RNJR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS54A20RNJR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS54A20RNJR reliable?
The price and inventory of TPS54A20RNJR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS54A20RNJR is usually 5 days.
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Once your TPS54A20RNJR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS54A20RNJR?
For technical support, including TPS54A20RNJR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS54A20RNJR requirements.
6.How does Aetrix verify that TPS54A20RNJR is sourced from the original manufacturer or authorized distributors?
All TPS54A20RNJR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS54A20RNJR meets industry standards.
7.What is the process for return or replacement of TPS54A20RNJR?
All TPS54A20RNJR units undergo pre-shipment inspection (PSI). If there is an issue with TPS54A20RNJR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS54A20RNJR part is unused and in its original packaging.
Return procedure for TPS54A20RNJR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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