Texas Instruments TPS5625PWP

Overview

TPS5625PWP from Texas Instruments is a synchronous-buck hysteretic regulator controller delivering 2.5 V fixed output with ±1% reference accuracy over 0°C to 125°C, 11.4–13 V VCC input range, and 2-A peak gate drivers for high-efficiency DSP power supplies. It features programmable soft-start, active deadtime control, and power-good monitoring.

For engineers reviewing the TPS5625PWP datasheet, TPS5625PWP pinout, TPS5625PWP application, or TPS5625PWP equivalent, key selection criteria include its 2.5 V fixed output, 250 ns propagation delay, hysteresis-adjustable transient response, and integrated overvoltage/overcurrent protection for robust 12-V-input DC-DC conversion.

Technical Context

The TPS5625PWP implements a user-configurable hysteretic control architecture centered on a buffered 2.5 V reference (VREFB), enabling fast load-transient response with <250 ns comparator-to-driver propagation delay. Its dual 2-A gate drivers support both bootstrap and ground-referenced high-side configurations.

Deadtime is actively enforced via LOHIB sensing of phase-node voltage, preventing shoot-through by ensuring low-side FET turn-on only after phase voltage drops below 2 V and high-side turn-on only after low-side gate voltage falls below 2 V. Overvoltage (115% VREF) and undervoltage (93% VREF) detection feed open-drain PWRGD and fault latching.

Key Specifications

Pinout & Package

TPS5625PWP is housed in a 28-pin TSSOP PowerPad™ (PWP) package with exposed thermal pad for enhanced power dissipation. The package supports tape-and-reel (suffix R) and operates from 0°C to 125°C junction temperature.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous-buck controller applications.

Compared with TPS5615PWP and TPS5633PWP, the TPS5625PWP provides the exact 2.5 V output needed for mid-voltage DSP cores and mixed-signal SoCs, preserving full compatibility in layout and firmware while optimizing regulation accuracy and transient headroom for that specific voltage domain.

Availability

TPS5625PWP is available at Aetrix Electronics and suitable for DSP power supplies, industrial 12-V converters, and telecom line card biasing requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for TPS5625PWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with decades of DC-DC controller innovation.

The TPS56xx family was designed specifically for high-efficiency, high-transient-response synchronous buck regulation in DSP and digital signal processing systems, emphasizing precision reference stability and robust gate drive capability.

FAQ

What output voltage does the TPS5625PWP provide?

The TPS5625PWP provides a fixed 2.5 V output voltage with ±1% accuracy over the full operating junction temperature range of 0°C to 125°C. This specification is guaranteed under 11.4 V to 13 V VCC supply conditions and is internally set by a precision resistive divider referenced to the bandgap. The TPS5625PWP does not support adjustable output; it is part of a pin-compatible family offering 1.5 V, 1.8 V, 2.5 V, and 3.3 V fixed options.

Does the TPS5625PWP support both bootstrap and ground-referenced high-side drive configurations?

Yes, the TPS5625PWP supports both configurations via the BOOT and BOOTLO pins. For bootstrap operation, BOOTLO connects to the phase node between high- and low-side FETs; for ground-referenced drive, BOOTLO connects to DRVGND and BOOT connects to DRV or VCC. The internal Schottky bootstrap diode (between DRV and BOOT) improves efficiency in floating mode, and the high-side driver delivers 2-A peak current in either configuration.

How is overcurrent protection implemented in the TPS5625PWP?

The TPS5625PWP implements overcurrent protection (OCP) by monitoring the voltage on the IOUT pin - which reflects 2×R_DS(on)×I_OUT - using an external resistor divider to the OCP pin. When OCP exceeds 100 mV (typical), a fault latch disables both drivers until VCC drops below UVLO. A 3-μs deglitch timer prevents false triggering, and the circuit also protects against high-side FET short-to-ground faults at the phase node.

What is the function of the INHIBIT pin on the TPS5625PWP?

The INHIBIT pin on the TPS5625PWP serves dual functions: it acts as a TTL-compatible enable/disable input (2.1 V typical startup threshold) and as an undervoltage lockout monitor for the system logic supply (3.3 V or 5 V). When pulled low, it discharges the soft-start capacitor and forces drivers low. When tied to the system logic rail, it ensures the TPS5625PWP remains disabled until both the 12-V VCC and logic supply exceed their respective UVLO thresholds.

Can the TPS5625PWP be used with external current-sense resistors for higher accuracy?

Yes, the TPS5625PWP supports external current-sense resistors for improved accuracy beyond its intrinsic high-side R_DS(on)-based sensing. The datasheet explicitly recommends placing a sense resistor in series with the high-side FET drain and connecting it to HISENSE and LOSENSE. The internal sample/hold circuit then measures voltage across this resistor, providing a more precise current representation than the 2×R_DS(on)×I_OUT approximation used on the IOUT pin.