Texas Instruments TPS5625PWPG4
- Part No.:
- TPS5625PWPG4
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 28-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS5625PWPG4.pdf
- Description:
- IC REG CTRLR DSP 1OUT 28HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,786
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS5625PWPG4 from Texas Instruments is a synchronous-buck hysteretic regulator controller delivering fixed 2.5 V output with ±1% reference accuracy over 0°C to 125°C junction temperature, 11.4–13 V VCC input, and integrated 2-A high- and low-side MOSFET drivers for DSP power supply applications.
For engineers reviewing the TPS5625PWPG4 datasheet, TPS5625PWPG4 pinout, TPS5625PWPG4 application, or TPS5625PWPG4 equivalent, key selection criteria include its user-selectable hysteresis control, active deadtime management, programmable soft-start, power-good monitoring, and overvoltage/overcurrent protection architecture.
Technical Context
The TPS5625PWPG4 implements a hysteretic control loop centered on a buffered 2.5 V reference (VREFB), with hysteresis set externally via resistor divider on VHYST to achieve fast transient response and <250 ns propagation delay from VSENSE to driver outputs. It integrates dual 2-A peak-current drivers supporting both bootstrap and ground-referenced high-side configurations.
Its analog subsystem includes a dedicated current-sensing path using high-side FET RDS(on) sampling (IOUT/IOUTLO), OCP threshold set via external resistor to OCP pin (90–110 mV trip), and independent UVLO (10 V start, 2 V hysteresis) and INHIBIT (2.1 V start, 100 mV hysteresis) comparators for robust power sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 2.5 V ±1% over 0°C to 125°C - ensures stable core voltage for DSPs without external feedback resistors. |
| VCC Input Range | 11.4 V to 13 V - designed for 12-V intermediate bus systems with tight regulation tolerance. |
| Driver Output Current | 2 A peak sink/source per side - drives low-RDS(on) n-channel MOSFETs directly without gate-driver ICs. |
| Hysteresis Control | User-configurable via VHYST pin (max 60 mV window) - enables load-transient optimization without loop compensation. |
| Power Good Threshold | 93% of VREF (±10 mV hysteresis) - open-drain PWRGD asserts when output drops below 2.325 V, enabling system reset coordination. |
| OCP Trip Voltage | 100 mV at OCP pin - sets overcurrent limit with external resistor divider; latch resets only on VCC UVLO recovery. |
| Soft-Start Timing | Programmable via capacitor on SLOWST pin - charging current derived from VREFB current (e.g., 100 μA → ~1 ms/μF). |
Pinout & Package
The TPS5625PWPG4 is housed in a 28-pin TSSOP PowerPad™ (PWP) package with exposed thermal pad for enhanced power dissipation. Pin 1 is IOUT; pin 28 is PWRGD. AGND2 and ANAGND are separate analog grounds requiring star-point connection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IOUT | Current-sense output | Provides voltage proportional to high-side FET conduction loss (2 × RDS(on) × IOUT) for OCP and telemetry. |
| VSENSE | Output voltage feedback | Direct connection to converter output bus; RC filter recommended for noise immunity in closed-loop regulation. |
| VREFB | Buffered reference output | 2.5 V ±2% source for hysteresis setting and soft-start timing; max 0.4 mA load to preserve accuracy. |
| HIGHDR / LOWDR | High-/low-side gate drivers | 2-A peak drive outputs with internal 8-V gate regulators; support bootstrap (BOOT/BOOTLO) or ground-referenced configuration. |
| PWRGD | Power-good monitor | Open-drain output pulled low when VOUT < 93% of 2.5 V - used for processor reset or enable sequencing. |
| INHIBIT | Enable & system UVLO input | TTL-compatible digital input; also monitors 3.3 V/5 V logic rail (2.1 V threshold) for safe power-up sequencing. |
Key Features
| Feature | Design Value |
|---|---|
| Synchronous rectifier driver | Integrated 2-A low-side driver eliminates external Schottky diode, enabling >90% efficiency in high-current buck stages. |
| Active deadtime control | Prevents shoot-through by enforcing minimum off-time between HIGHDR and LOWDR transitions based on phase-node voltage. |
| Programmable soft-start | Capacitor-controlled ramp on SLOWST pin avoids inrush current; timing determined by VREFB sourcing current into CSLOWST. |
| Overvoltage protection | Disables drivers if VOUT exceeds 115% of 2.5 V (2.875 V); 3-μs deglitch prevents false triggering from noise. |
| Hysteretic-type control | User-selectable hysteresis reduces load-step overshoot/undershoot without requiring external compensation components. |
Applications
| DSP Core Power Supply | Telecom Line Card Bias |
|---|---|
Use Scenario: Providing tightly regulated 2.5 V to TI C6000-series DSPs in baseband processing units with rapid load transients. IC Role / Device Role / Timing Role: Primary buck controller managing high-side/low-side FET switching, current sensing, and power sequencing. Use Value: ±1% output accuracy and <250 ns propagation delay ensure stable operation during 10-A load steps typical in real-time signal processing. | Use Scenario: Generating 2.5 V bias for analog front-end (AFE) circuits in multi-channel telecom line cards operating in extended temperature environments. IC Role / Device Role / Timing Role: Regulator controller with integrated drivers and thermal robustness for unattended field deployment. Use Value: 0°C to 125°C junction rating and active deadtime control prevent shoot-through failures under thermal stress and variable load conditions. |
| Industrial PLC I/O Module | Test Equipment Power Rail |
Use Scenario: Delivering clean, sequenced 2.5 V to FPGA configuration banks and ADC reference buffers in programmable logic controllers. IC Role / Device Role / Timing Role: Controller with INHIBIT-driven power sequencing and PWRGD status reporting for system-level fault isolation. Use Value: Dual UVLO (VCC + INHIBIT) guarantees startup only after both 12 V and 3.3 V rails are valid, preventing configuration corruption. | Use Scenario: Serving as adjustable 2.5 V source in automated test equipment where output stability and fast transient recovery are critical for measurement integrity. IC Role / Device Role / Timing Role: Hysteretic controller with programmable hysteresis enabling optimized trade-off between ripple and response speed. Use Value: External hysteresis tuning allows designers to reduce output ripple to <15 mV while maintaining <1 μs recovery from 50% load steps. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous-buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS5625PWPR | Same silicon, tape-and-reel packaging (R suffix); identical electrical specs and pinout. | No functional difference; selected for automated SMT assembly vs. tube delivery. | Choose TPS5625PWPR for volume production; TPS5625PWPG4 is tube-packaged for prototyping and low-volume builds. |
| TPS5618PWPG4 | Identical architecture and package, but fixed 1.8 V output; shares same VCC range, driver strength, and protection features. | Used where lower core voltage is required (e.g., newer DSPs or FPGAs), not drop-in compatible for 2.5 V systems. | Select TPS5618PWPG4 only when target application requires 1.8 V; no PCB change needed, but output voltage is fixed and non-adjustable. |
Compared with TPS5625PWPG4, TPS5625PWPR offers identical performance in tape-and-reel format for manufacturing scalability, while TPS5618PWPG4 provides architectural parity at 1.8 V-making it suitable for voltage-scaling upgrades without redesigning driver or protection circuitry.
Availability
TPS5625PWPG4 is available at Aetrix Electronics and suitable for DSP power supplies, telecom line card biasing, industrial PLC I/O modules, and test equipment power rails requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for TPS5625PWPG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with broad industrial and automotive qualification.
The TPS56xx family was engineered specifically for high-efficiency, high-transient-response DC/DC conversion in digital signal processor power systems, emphasizing integration, thermal resilience, and robust fault protection.
FAQ
What is the output voltage tolerance of the TPS5625PWPG4 over temperature?
The TPS5625PWPG4 delivers a fixed 2.5 V output with ±1% accuracy across its full operating junction temperature range of 0°C to 125°C. This specification is guaranteed under VCC = 11.4 V to 12.6 V and reflects the internal resistive divider's precision and bandgap reference stability. The buffered VREFB pin provides this reference with ±2% tolerance and must not be loaded beyond 0.4 mA to maintain timing and hysteresis accuracy in the TPS5625PWPG4.
Does the TPS5625PWPG4 support both bootstrap and ground-referenced high-side drive configurations?
Yes, the TPS5625PWPG4 supports both configurations. For bootstrap operation, connect BOOT to the high-side FET drain and BOOTLO to the source node (phase node); for ground-referenced drive, tie BOOTLO to DRVGND and connect BOOT to DRV or VCC. The internal Schottky bootstrap diode (between DRV and BOOT) enables efficient charge transfer in floating mode, while the 30-V absolute maximum BOOT-to-DRVGND rating ensures safe operation in either topology within the TPS5625PWPG4.
How is overcurrent protection implemented in the TPS5625PWPG4?
The TPS5625PWPG4 implements overcurrent protection (OCP) by monitoring the voltage at the OCP pin, which is fed from a resistor divider between IOUT and ANAGND. When the OCP pin voltage exceeds 100 mV (90–110 mV range), a fault latch disables both HIGHDR and LOWDR outputs. Recovery requires VCC to fall below the UVLO stop threshold (~7.5 V). A 3-μs deglitch timer prevents false triggering from noise, and the OCP circuit also protects against high-side FET short-to-ground faults at the phase node in the TPS5625PWPG4.
What is the purpose of the INHIBIT pin on the TPS5625PWPG4?
The INHIBIT pin serves dual functions: it acts as a TTL-compatible enable/disable input for the controller and as an undervoltage lockout (UVLO) monitor for the system logic supply (3.3 V or 5 V). When pulled low, it disables all drivers and discharges the soft-start capacitor. Its 2.1 V start threshold and 100 mV hysteresis ensure coordinated startup only after both the 12-V VCC rail and the logic rail are valid-critical for reliable power sequencing in complex systems using the TPS5625PWPG4.
Can the TPS5625PWPG4 be used with external current-sense resistors instead of RDS(on) sensing?
Yes, the TPS5625PWPG4 supports external current-sense resistors for higher accuracy. While the default method samples voltage across the high-side FET's RDS(on) (via IOUT/IOUTLO), the datasheet explicitly describes an alternative scheme: place a sense resistor in series with the high-side FET drain and connect HISENSE to the supply side and LOSENSE to the FET drain side. This configuration bypasses RDS(on) variation and improves current measurement fidelity in precision applications using the TPS5625PWPG4.
TPS5625PWPG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 28-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Applications:
- Controller, DSP
- Voltage - Input:
- 11.4V ~ 13V
- Number of Outputs:
- 1
- Voltage - Output:
- 2.5V
- Operating Temperature:
- 0°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-HTSSOP
TPS5625PWPG4 FAQ
1.How can I place an order for TPS5625PWPG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS5625PWPG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS5625PWPG4 reliable?
The price and inventory of TPS5625PWPG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS5625PWPG4 is usually 5 days.
3.What payment methods are accepted for TPS5625PWPG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS5625PWPG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS5625PWPG4?
TPS5625PWPG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS5625PWPG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS5625PWPG4?
For technical support, including TPS5625PWPG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS5625PWPG4 requirements.
6.How does Aetrix verify that TPS5625PWPG4 is sourced from the original manufacturer or authorized distributors?
All TPS5625PWPG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS5625PWPG4 meets industry standards.
7.What is the process for return or replacement of TPS5625PWPG4?
All TPS5625PWPG4 units undergo pre-shipment inspection (PSI). If there is an issue with TPS5625PWPG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS5625PWPG4 part is unused and in its original packaging.
Return procedure for TPS5625PWPG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS5625PWPG4 Tags

-
TPS51206DSQR
Texas Instruments

-
TPS51200DRCR
Texas Instruments

-
TPS51200DRCT
Texas Instruments

-
TPS62740DSSR
Texas Instruments

-
TPS51100DGQR
Texas Instruments
-
NCP51200MNTXG
onsemi
-
NCP51400MNTXG
onsemi

-
RT9026GSP
Richtek USA Inc.

-
LP2998MRX/NOPB
Texas Instruments

-
TPS51200QDRCRQ1
Texas Instruments

-
DPA423GN-TL
Power Integrations

-
LM10011SD/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

