Texas Instruments TPS564255DRLR

Overview

TPS564255DRLR from Texas Instruments is a 4-A synchronous buck converter in SOT-563 package, operating from 3 V to 17 V input and delivering 0.6 V to 10 V output with ±1% reference accuracy at 25°C. It integrates 55.0-mΩ high-side and 24.3-mΩ low-side MOSFETs, uses D-CAP3™ control mode for fast transient response, and features Out-of-Audio™ (OOA) light-load operation to suppress audible noise - deployed in Wi-Fi routers and smart speakers.

For engineers reviewing the TPS564255DRLR datasheet, TPS564255DRLR pinout, TPS564255DRLR application, or TPS564255DRLR equivalent, key selection criteria include OOA-mode switching behavior above 25 kHz at light load, integrated bootstrap capacitor enabling single-layer PCB layout, 1.6-ms fixed soft-start, open-drain power-good indicator, and non-latch thermal/overcurrent/UVLO protection with hiccup recovery.

Technical Context

The TPS564255DRLR implements D-CAP3™ adaptive on-time control with internal ripple emulation, eliminating external compensation and supporting ultra-low-ESR ceramic capacitors. Its OOA mode actively prevents switching frequency from dropping into the audible range (<25 kHz) by forcing periodic low-side conduction when idle >30 µs.

It delivers up to 97% duty cycle via frequency foldback (down to ~200 kHz), supports prebiased output startup, and integrates full protection: cycle-by-cycle overcurrent (valley detect), output overvoltage (115% trip, 24 µs deglitch), undervoltage (60% trip, 220 µs deglitch + 14 ms hiccup enable), and thermal shutdown (155°C, 20°C hysteresis).

Key Specifications

Pinout & Package

TPS564255DRLR is housed in a 1.6 mm × 1.6 mm, 6-pin SOT-563 (DRL) package with exposed thermal pad (not electrically connected). The small footprint supports high-density layouts and reduces parasitic inductance in switch-node routing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck converter applications.

Compared with TPS564252DRLR and TPS564257DRLR, the TPS564255DRLR uniquely prioritizes acoustic silence over IQ or ripple - making it the sole choice when coil whine must be eliminated in always-on consumer audio/video products.

Availability

TPS564255DRLR is available at Aetrix Electronics and suitable for WLAN infrastructure, smart speaker power delivery, and surveillance camera systems requiring stable component supply, long-term lifecycle support, and guaranteed authentic sourcing.

Supply support for TPS564255DRLR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-efficiency DC/DC conversion.

The TPS56425x family was designed specifically for space-constrained, noise-sensitive consumer and industrial applications requiring integrated 4-A buck solutions with simplified layout and robust protection - exemplified by the OOA-focused TPS564255DRLR variant.

FAQ

What is the primary functional distinction of TPS564255DRLR versus other TPS56425x variants?

The TPS564255DRLR implements Out-of-Audio™ (OOA) mode, which actively forces switching frequency above 25 kHz under all load conditions - unlike TPS564252DRLR (Eco-mode, variable frequency down to ~10 kHz) or TPS564257DRLR (FCCM, fixed 600 kHz). This prevents audible coil whine in audio-critical applications such as smart speakers and pro-audio gear, making TPS564255DRLR the only variant optimized for acoustic silence.

Does TPS564255DRLR support prebiased output startup, and how does it behave during this condition?

Yes, TPS564255DRLR supports prebiased output startup. When the FB pin voltage exceeds the internal reference at EN assertion, the device delays switching until the internal soft-start ramp rises above the prebiased FB level. This prevents reverse current flow through the low-side MOSFET and avoids output voltage overshoot or instability - critical for hot-swap and modular power system designs using TPS564255DRLR.

What is the maximum achievable duty cycle for TPS564255DRLR, and under what conditions does it activate?

The TPS564255DRLR supports up to 97% duty cycle via adaptive frequency foldback. This occurs when VIN/VOUT < 1.6 and FB falls below VREF - for example, during 12 V → 3.3 V conversion at heavy load. Switching frequency smoothly decreases to ~200 kHz to extend t_ON, maintaining regulation without dropout. The feature is inherent to D-CAP3 control and requires no external configuration in TPS564255DRLR.

How does the power-good (PG) pin of TPS564255DRLR respond to output voltage deviations?

The PG pin of TPS564255DRLR is an open-drain indicator asserting low when FB drops below 85% VREF (falling) or rises above 115% VREF (rising), with 1 ms delay on rising edge and 28 µs on falling edge. It remains high during normal regulation (85–115% VREF window) and provides precise sequencing feedback - essential for coordinating TPS564255DRLR with FPGA or SoC power-on reset logic.

Can TPS564255DRLR operate with ceramic output capacitors only, and what is the minimum recommended capacitance?

Yes, TPS564255DRLR is fully compatible with ceramic output capacitors due to its D-CAP3™ control architecture, which emulates ripple internally. No external ESR is required. For stable operation at 4 A, TI recommends ≥22 µF total ceramic capacitance (e.g., four 4.7 µF X5R 0805s in parallel) placed close to the FB and SW pins - verified in TPS564255DRLR evaluation designs and characteristic curves.