Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Special Purpose Regulators

Texas Instruments TPS59116RGER

Name: TPS59116RGER
Brand: Texas Instruments
SKU: TPS59116RGER
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: TPS59116RGER

Manufacturer:: Texas Instruments

Category:: Special Purpose Regulators

Package:: 24-VFQFN Exposed Pad

Datasheet:: TPS59116RGER.pdf

Description:: IC REG CTRLR DDR 2OUT 24VQFN

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,522

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

TPS59116RGER from Texas Instruments is a complete DDR/DDR2/DDR3 memory power solution integrating a 400-kHz synchronous buck controller (VDDQ), a 3-A sink/source LDO (VTT), and a buffered ±20-mV-accurate 10-mA reference (VTTREF). It delivers 2.5 V / 1.8 V / adjustable 0.75–3.0 V VDDQ output, supports R_DS(on) or resistor current sensing, and enables S3 high-Z and S4/S5 soft-off discharge control for embedded computing systems.

For engineers reviewing the TPS59116RGER datasheet, TPS59116RGER pinout, TPS59116RGER application, or TPS59116RGER equivalent, key selection considerations include its dual-mode D-CAP™/current-mode control, 100-ns load-step response, VTT's 3-A bidirectional capability with only 20-μF ceramic output capacitance, and JEDEC-compliant S3/S4/S5 state management for DDR memory subsystems.

Technical Context

The TPS59116RGER implements adaptive on-time PWM control with fixed 400-kHz pseudo-constant frequency operation, selectable via COMP pin connection (D-CAP™ mode when tied to V5IN; current mode otherwise). Its transconductance amplifier provides programmable compensation in current mode, while D-CAP™ eliminates external compensation components.

VDDQ regulation uses VDDQSNS for feedback and VDDQSET for voltage selection (GND = 2.5 V, V5IN = 1.8 V, resistor divider = adjustable). The integrated VTT LDO employs remote sensing via VTTSNS, supports tracking discharge (via internal LDO transistors) or non-tracking discharge (via dedicated FETs), and maintains ±40 mV accuracy at full 3-A load.

Key Specifications

Parameter	Value and Actual Design Meaning
VDDQ Output Voltage	Configurable: 2.5 V (DDR), 1.8 V (DDR2), or 0.75–3.0 V (DDR3/LPDDR3) - set by VDDQSET pin logic or resistor divider
VTT Output Capability	±3 A sink/source with ±40 mV regulation accuracy at full load - enables active termination without external op-amps or discrete FETs
Control Modes	D-CAP™ (100-ns load step response, no external compensation) or current mode (supports ceramic capacitors with near-zero ESR)
Current Sensing	Dual-scheme: R_DS(on) of bottom MOSFET (lossless, temperature-compensated ITRIP) or external sense resistor (higher accuracy)
Sleep State Control	S3: VTT high-Z; S4/S5: VDDQ/VTT/VTTREF soft-off with tracking or non-tracking discharge - fully compliant with JEDEC DDR/DDR2 specifications
VTTREF Accuracy	±20 mV at no load, tracks VDDQ/2 within ±1% - provides low-noise, buffered reference for SSTL/HSTL termination
Package	24-pin QFN (4 mm × 4 mm, 0.5-mm pitch) with exposed thermal pad - optimized for thermal performance in space-constrained memory power rails

Pinout & Package

TPS59116RGER is housed in a thermally enhanced 24-pin QFN package (4 mm × 4 mm, 0.5-mm pitch) with an exposed thermal pad for efficient heat dissipation in DDR memory power applications.

Pin/Terminal	Circuit Role	Design Meaning
V5IN (Pin 15)	5-V gate driver supply input	Provides bias for DRVH/DRVL drivers; must be decoupled with ≥10 μF ceramic capacitor
DRVH (Pin 21)	High-side N-MOSFET gate driver output	Drives top switch with 0.9–3 Ω pull-down/pull-up resistance; requires bootstrap capacitor (VBST–LL)
DRVL (Pin 19)	Low-side N-MOSFET gate driver output	Drives bottom switch with 0.9–3 Ω pull-down/pull-up resistance; dead time prevents shoot-through
VDDQSNS (Pin 8)	VDDQ output voltage sense and VTTREF source	Feeds internal ½-divider for VTTREF; also used as feedback node when VDDQSET is grounded or tied to V5IN
VTTSNS (Pin 2)	VTT output remote sense input	Enables Kelvin sensing to reject PCB trace IR drop; must connect directly to + terminal of VTT output capacitor
S3 / S5 (Pins 10/11)	JEDEC sleep-state control inputs	Directly interface to system SLP_S3/SLP_S5 signals to manage VTT high-Z (S3) and soft-off discharge (S4/S5)
MODE (Pin 4)	VDDQ/VTT discharge mode select	Selects tracking (LDO-based) vs. non-tracking (dedicated FET) discharge path during S4/S5 states
PGOOD (Pin 13)	Open-drain power-good indicator	Asserts high when VDDQ is within ±2.5% of target; 2.5–7.5 mA sink capability for pull-up resistor selection

Key Features

Feature	Design Value
D-CAP™ adaptive on-time control	Delivers 100-ns load transient response without external compensation components - reduces BOM count and layout complexity
VTT bidirectional 3-A LDO	Eliminates need for separate sourcing/sinking regulators; maintains ±40 mV accuracy with only 20-μF (2×10 μF) ceramic output capacitance
Buffered VTTREF output	10-mA, ±20-mV-accurate, low-noise reference derived from VDDQ/2 - supports SSTL-2, SSTL-18, and HSTL termination without external buffers
JEDEC-compliant S3/S4/S5 control	Hardware-managed state transitions: S3 floats VTT, S4/S5 discharges VDDQ/VTT/VTTREF - ensures DDR timing compliance without firmware intervention
R_DS(on) current sensing	Integrates 4500 ppm/°C temperature-compensated ITRIP current source - enables lossless, cost-effective current limit without sense resistors

Applications

DDR Memory Power Supply	SSTL-18 Termination
Use Scenario: Powering DDR2 memory modules in industrial embedded controllers requiring stable 1.8-V VDDQ and matched VTT termination. IC Role / Device Role / Timing Role: TPS59116RGER serves as the primary VDDQ buck controller and VTT active terminator, synchronizing startup/shutdown sequencing per JEDEC spec. Use Value: Eliminates discrete VTT regulator and reference ICs; achieves ±40 mV VTT regulation at 2-A load using only 20-μF ceramic capacitance.	Use Scenario: Providing precise 0.9-V VTT and buffered 0.9-V VTTREF for SSTL-18 I/O interfaces in FPGA-based communication baseboards. IC Role / Device Role / Timing Role: TPS59116RGER generates tightly tracked VTT/VTTREF from VDDQSNS, enabling clean signal integrity on high-speed parallel buses. Use Value: Delivers ±20-mV VTTREF accuracy and <100-ns VDDQ load-step response - critical for maintaining setup/hold margins in 400-MHz DDR2 interfaces.
DDR3 Adjustable VDDQ Supply	LPDDR3 Mobile Memory Power
Use Scenario: Configuring 1.5-V VDDQ for DDR3L memory in thin-client laptops using external resistor divider on VDDQSET pin. IC Role / Device Role / Timing Role: TPS59116RGER operates in adjustable mode with VDDQSET feedback, while managing VTT discharge during S3 suspend-to-RAM cycles. Use Value: Supports DDR3 voltage scaling via precision 750-mV internal reference; VTT high-Z in S3 reduces standby power by >95% vs. always-on termination.	Use Scenario: Delivering 1.2-V VDDQ and 0.6-V VTT for LPDDR3 memory in portable medical imaging devices with strict thermal constraints. IC Role / Device Role / Timing Role: TPS59116RGER leverages QFN-24 thermal pad and adaptive light-load frequency reduction to maintain <2.2 W power dissipation at 85°C ambient. Use Value: Achieves >90% efficiency at 1-A load via discontinuous conduction mode transition; VLDOIN pin allows VTT supply from lower intermediate rail to cut power loss.

DDR Memory Power Supply

SSTL-18 Termination

Use Scenario: Powering DDR2 memory modules in industrial embedded controllers requiring stable 1.8-V VDDQ and matched VTT termination.

IC Role / Device Role / Timing Role: TPS59116RGER serves as the primary VDDQ buck controller and VTT active terminator, synchronizing startup/shutdown sequencing per JEDEC spec.

Use Value: Eliminates discrete VTT regulator and reference ICs; achieves ±40 mV VTT regulation at 2-A load using only 20-μF ceramic capacitance.

Use Scenario: Providing precise 0.9-V VTT and buffered 0.9-V VTTREF for SSTL-18 I/O interfaces in FPGA-based communication baseboards.

IC Role / Device Role / Timing Role: TPS59116RGER generates tightly tracked VTT/VTTREF from VDDQSNS, enabling clean signal integrity on high-speed parallel buses.

Use Value: Delivers ±20-mV VTTREF accuracy and <100-ns VDDQ load-step response - critical for maintaining setup/hold margins in 400-MHz DDR2 interfaces.

DDR3 Adjustable VDDQ Supply

LPDDR3 Mobile Memory Power

Use Scenario: Configuring 1.5-V VDDQ for DDR3L memory in thin-client laptops using external resistor divider on VDDQSET pin.

IC Role / Device Role / Timing Role: TPS59116RGER operates in adjustable mode with VDDQSET feedback, while managing VTT discharge during S3 suspend-to-RAM cycles.

Use Value: Supports DDR3 voltage scaling via precision 750-mV internal reference; VTT high-Z in S3 reduces standby power by >95% vs. always-on termination.

Use Scenario: Delivering 1.2-V VDDQ and 0.6-V VTT for LPDDR3 memory in portable medical imaging devices with strict thermal constraints.

IC Role / Device Role / Timing Role: TPS59116RGER leverages QFN-24 thermal pad and adaptive light-load frequency reduction to maintain <2.2 W power dissipation at 85°C ambient.

Use Value: Achieves >90% efficiency at 1-A load via discontinuous conduction mode transition; VLDOIN pin allows VTT supply from lower intermediate rail to cut power loss.

Equivalent & Alternatives

The following parts are listed as comparable options for similar DDR memory power management applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPS51216RGET	Single-channel 3-A VDDQ controller only; no integrated VTT LDO or VTTREF - requires external VTT solution	Targeted at designs where VTT is implemented separately (e.g., discrete FET + op-amp); lacks S3/S4/S5 hardware control	Choose when board area allows separate VTT regulation and JEDEC sleep-state automation is not required.
ISL6537CRZ	Legacy dual-output controller (VDDQ + VTT) with 2-A VTT sink-only capability; no VTTREF buffer; supports only DDR/DDR2 voltages	Designed for older DDR2 platforms; lacks DDR3 adjustability, D-CAP™ mode, and modern thermal QFN packaging	Consider only for legacy DDR2 redesigns where footprint compatibility and long-term availability outweigh performance gaps.

Compared with TPS51216RGET and ISL6537CRZ, the TPS59116RGER uniquely integrates full DDR/DDR2/DDR3 support, bidirectional 3-A VTT, buffered VTTREF, and hardware-enforced JEDEC sleep states in a single QFN package - reducing component count by ≥4 ICs and eliminating manual sequencing firmware.

Availability

TPS59116RGER is available at Aetrix Electronics and suitable for DDR3 server DIMMs, DDR2 industrial HMIs, and LPDDR3 mobile edge AI accelerators requiring stable component supply, JEDEC-compliant power sequencing, and high-efficiency memory rail regulation.

Supply support for TPS59116RGER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management ICs for computing and communications infrastructure.

The TPS59116 product line was designed specifically to consolidate DDR/DDR2/DDR3 memory power into one IC - targeting space-constrained embedded systems needing JEDEC-compliant sequencing, fast transient response, and minimal external components.

FAQ

What is the maximum supported input voltage for the TPS59116RGER synchronous buck controller?

The TPS59116RGER synchronous buck controller supports an input voltage range of 3.0 V to 28 V on the VIN path (monitored at LL pin). This wide range accommodates 5-V, 12-V, and 24-V intermediate bus architectures common in servers, industrial PCs, and networking equipment using the TPS59116RGER.

How does the TPS59116RGER achieve ±40 mV VTT regulation accuracy at 3-A load?

The TPS59116RGER achieves ±40 mV VTT regulation at full 3-A load through a combination of remote sensing (VTTSNS pin connected to VTT capacitor positive terminal), high-bandwidth error amplifier design, and optimized loop compensation. Its integrated LDO architecture maintains tight tracking to VTTREF even under fast load transients, validated across -40°C to 85°C.

Can the TPS59116RGER be configured for DDR3L (1.35 V) VDDQ output?

Yes, the TPS59116RGER supports DDR3L VDDQ output via its adjustable mode: connect an external resistor divider to VDDQSET to set VDDQ between 0.75 V and 3.0 V. For 1.35 V, use standard feedback resistor values referenced to the internal 750-mV reference - confirmed in TI's SLUSA57 datasheet Table 1.

What is the purpose of the MODE pin on the TPS59116RGER, and how does it affect discharge behavior?

The MODE pin on the TPS59116RGER selects between tracking discharge (MODE = high) and non-tracking discharge (MODE = low) during S4/S5 states. Tracking discharge uses internal LDO transistors for faster, controlled ramp-down; non-tracking uses dedicated discharge FETs for slower, lower-current discharge - both ensure safe memory power-down per JEDEC requirements.

Does the TPS59116RGER require external compensation components in D-CAP™ mode?

No, the TPS59116RGER requires no external compensation components in D-CAP™ mode: connecting the COMP pin to V5IN disables the transconductance amplifier and activates the internal zero-pole compensation network. This simplifies layout and reduces BOM count while delivering 100-ns load-step response - a core feature of the TPS59116RGER design.

TPS59116RGER Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: D-CAP™

Package/Case:: 24-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Applications:: Controller, DDR

Voltage - Input:: 3V ~ 28V

Number of Outputs:: 2

Voltage - Output:: 0.76V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 24-VQFN (4x4)

TPS59116RGER FAQ

1.How can I place an order for TPS59116RGER through Aetrix?

Please submit a Request for Quotation (RFQ) for TPS59116RGER on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for TPS59116RGER reliable?

The price and inventory of TPS59116RGER are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS59116RGER is usually 5 days.

3.What payment methods are accepted for TPS59116RGER?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS59116RGER transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for TPS59116RGER?

TPS59116RGER orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your TPS59116RGER order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for TPS59116RGER?

For technical support, including TPS59116RGER datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS59116RGER requirements.

6.How does Aetrix verify that TPS59116RGER is sourced from the original manufacturer or authorized distributors?

All TPS59116RGER products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS59116RGER meets industry standards.

7.What is the process for return or replacement of TPS59116RGER?

All TPS59116RGER units undergo pre-shipment inspection (PSI). If there is an issue with TPS59116RGER, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The TPS59116RGER part is unused and in its original packaging.

Return procedure for TPS59116RGER:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…