Texas Instruments TPS59116RGET

Overview

TPS59116RGET from Texas Instruments is a complete DDR/DDR2/DDR3 memory power solution integrating a synchronous buck controller (VDDQ), 3-A sink/source LDO (VTT), and buffered 10-mA reference (VREF). It delivers 2.5 V / 1.8 V / adjustable 0.75–3.0 V VDDQ output, ±20 mV VTT accuracy at no load, and supports D-CAP™ or current-mode control with 400-kHz pseudo-constant frequency. Used in embedded computing systems requiring JEDEC-compliant S3/S4/S5 sleep-state management.

For engineers reviewing the TPS59116RGET datasheet, TPS59116RGET pinout, TPS59116RGET application, or TPS59116RGET equivalent, key selection factors include VDDQ output voltage programmability, VTT's 3-A bidirectional capability, integrated soft-off discharge control, RDS(on)/resistor current sensing options, and QFN-24 package thermal performance under high transient loads.

Technical Context

The TPS59116RGET implements adaptive on-time PWM control with dual-mode operation: D-CAP™ mode (COMP tied to V5IN) enables 100-ns load-step response and minimal external components; current-mode operation (COMP floating or externally compensated) supports ceramic output capacitors with ultra-low ESR. Its transconductance amplifier provides 240–360 μS gain for stable loop compensation.

VDDQ regulation uses VDDQSNS for feedback and VDDQSET for voltage selection (GND = 2.5 V, V5IN = 1.8 V, resistor divider = adjustable). The VTT LDO accepts VLDOIN as an independent input to reduce power loss during sourcing, and VTTSNS enables remote sensing for ±40 mV regulation across 0–3 A load range.

Key Specifications

Pinout & Package

TPS59116RGET is housed in a thermally enhanced 24-pin QFN package (4 mm × 4 mm, 0.5-mm pitch) with exposed thermal pad. Pin 1 is marked by dot; pin numbering follows standard counter-clockwise sequence starting from top-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar DDR memory power management applications.

Compared with TPS59116RGET, TPS51216RUKR reduces integration but increases BOM count and layout complexity for VTT, while ISL6322HRZ offers superior VDDQ current capacity at the cost of missing native VTT/VTTREF and JEDEC sleep-state control-making TPS59116RGET optimal for space-constrained embedded DDR designs requiring full power rail integration.

Availability

TPS59116RGET is available at Aetrix Electronics and suitable for DDR3 memory power supplies, SSTL-18 termination systems, and LPDDR3 mobile platform power management requiring stable component supply, long-term lifecycle assurance, and JEDEC-compliant sleep-state sequencing.

Supply support for TPS59116RGET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in memory interface power solutions.

The TPS59116 product line delivers fully integrated DDR/DDR2/DDR3 power management in compact packages, designed specifically for space-constrained embedded computing systems requiring JEDEC-compliant S3/S4/S5 control and high-efficiency transient response.

FAQ

What is the maximum supported VDDQ output voltage for TPS59116RGET?

The TPS59116RGET supports an adjustable VDDQ output range from 0.75 V to 3.0 V. Fixed outputs include 2.5 V (for DDR) and 1.8 V (for DDR2), selected by tying VDDQSET to GND or V5IN respectively. For DDR3, the device is configured via external resistor divider on VDDQSET to deliver 1.5 V, and the same configuration enables any value in the 0.75–3.0 V span. The TPS59116RGET datasheet specifies ±50 mV total output tolerance across temperature and load for adjustable modes.

How does TPS59116RGET manage VTT during S3 suspend-to-RAM state?

In S3 state (S3 = LOW, S5 = HIGH), the TPS59116RGET disables the VTT LDO output and places it in high-impedance (high-Z) mode, preventing any sourcing or sinking current. VDDQ and VTTREF remain active to maintain memory retention voltage. This behavior is hardware-controlled and requires no software intervention-ensuring deterministic low-power operation per JEDEC specification. The TPS59116RGET achieves this using internal logic that disconnects the VTT pass element while maintaining bias on VTTREF and VDDQ regulation loops.

Can TPS59116RGET use ceramic output capacitors for the VDDQ buck stage?

Yes, the TPS59116RGET supports ceramic output capacitors for the VDDQ buck stage in current-mode control configuration. When COMP is left floating or externally compensated, the device operates in current-mode, which provides stability with ultra-low-ESR ceramics. In D-CAP™ mode (COMP tied to V5IN), the internal compensation is optimized for capacitors with moderate ESR-typically polymer or tantalum-but ceramic use is still viable with careful layout and optional small series resistance. The TPS59116RGET datasheet confirms stable operation with 2×10-μF ceramic capacitors on VTT and recommends ≥20-μF total for VDDQ depending on control mode.

What is the purpose of the VLDOIN pin on TPS59116RGET?

The VLDOIN pin on TPS59116RGET supplies power to the VTT LDO's internal pass transistor driver stage. Connecting VLDOIN to a voltage lower than VDDQ-such as a dedicated 1.2-V rail or a post-regulated output-reduces power dissipation during VTT sourcing, especially when VTT = VDDQ/2. For example, with VDDQ = 1.5 V and VTT = 0.75 V, supplying VLDOIN = 0.9 V instead of 1.5 V cuts conduction loss by ~45%. The TPS59116RGET datasheet specifies VLDOIN operating range as –0.1 V to 3.6 V and confirms 20-μF ceramic output capacitance suffices regardless of VLDOIN source.

Does TPS59116RGET provide overvoltage and undervoltage protection for VDDQ?

Yes, the TPS59116RGET includes dedicated VDDQ overvoltage protection (OVP) and undervoltage protection (UVP) circuits. OVP triggers at 110–120% of nominal VDDQ (e.g., 2.75–3.0 V for 2.5-V setting) with 5% hysteresis and 1.5-μs propagation delay. UVP activates at 70% of nominal VDDQ (e.g., 1.75 V for 2.5-V setting) with 10% hysteresis and 32-cycle enable delay. Both protections force immediate shutdown of the VDDQ buck stage and assert PGOOD LOW. These functions are fully hardware-based and require no external components-integral to the TPS59116RGET's safety architecture for memory rail integrity.