Texas Instruments TPS59650RSLR
- Part No.:
- TPS59650RSLR
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Regulators
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
TPS59650RSLR.pdf
- Description:
- IC REG CTRLR IMVP-7 2OUT 48VQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS59650RSLR from Texas Instruments is a dual-channel IMVP-7-compliant step-down controller integrating two gate drivers for 3-phase CPU and 2-phase GPU power delivery. It supports SVID interface, D-CAP+™ control architecture, 8-bit DAC (0.250–1.52 V), adjustable voltage positioning, and operates across –40°C to 105°C in a 48-pin QFN package. It delivers fast transient response for notebook and ultrabook VCORE applications with adapter/battery/NVDC input rails.
For engineers reviewing the TPS59650RSLR datasheet, TPS59650RSLR pinout, TPS59650RSLR application, or TPS59650RSLR equivalent, key selection criteria include IMVP-7 compliance, integrated driver capability per channel, selectable 8-level current limit, dual PGOOD/VR_HOT signaling, and thermal monitoring via CTHERM/GTHERM pins for CPU/GPU rail stability.
Technical Context
The TPS59650RSLR implements D-CAP+™ control with overlapping pulse support for undershoot reduction (USR) and overshoot reduction (OSR), enabling low-output-capacitance designs and high efficiency across light-to-heavy loads. Its dual-channel architecture independently manages CPU (1-/2-/3-phase) and GPU (1-/2-phase) outputs using separate feedback loops (CVFB/GVFB), droop amplifiers (GM-DROOP), and phase-balancing logic (AutoBalance™).
It integrates two high-speed FET drivers (CDH1/CDL1/CDH2/CDL2 for CPU; CPWM3/GPWM1/GPWM2/GSKIP for GPU external driver control) and supports full IMVP-7 I/O including VR_ON, ALERT, PGOOD, VR_HOT, and SVID clock/data lines. The device latches configuration at startup via resistor-programmed pins (CF-IMAX, COCP-R, GF-IMAX, GOCP-R, SLEWA) and uses VREF (1.700 V ±0.045 V) as reference for DAC and sensing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Topology | Dual-channel synchronous buck controller with integrated CPU drivers and GPU PWM/SKIP outputs |
| Input Voltage Range | 3 V to 28 V - supports adapter, battery, and NVDC input rails without pre-regulation |
| Output Voltage Range | 0.250 V to 1.52 V via 8-bit SVID DAC - meets IMVP-7 VCORE specification |
| Operating Temperature | –40°C to 105°C - qualified for industrial-grade mobile platform operation |
| Package | 48-pin QFN (6 mm × 6 mm, PowerPAD™) - thermally enhanced for high-current CPU/GPU stages |
| Control Architecture | D-CAP+™ with USR/OSR - reduces output capacitance by >30% vs. conventional PID control |
| Current Sensing | Resistor- or DCR-based, dual-channel independent sense (CCSP1/CCSN1 + GCSP1/GCSN1) |
| Protection Features | OVP/UVP on xVFB, thermal shutdown at 155°C, VR_HOT/ALERT fault signaling, soft-stop via CVFB discharge |
Pinout & Package
TPS59650RSLR is housed in a thermally optimized 48-pin QFN (RSL package) with exposed PowerPAD™ for PCB heat dissipation. Pin functions are fully defined per TI SLUSAV7 datasheet, with dedicated CPU/GPU sensing, drive, feedback, and SVID interface terminals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CDH1 / CDL1 / CDH2 / CDL2 | CPU high-side/low-side gate drive outputs | Drive internal N-FETs for first two CPU phases; enable high-efficiency 3-phase operation with external TPS51601 for third phase |
| CPWM3 / GPWM1 / GPWM2 / GSKIP | GPU PWM and skip-mode control outputs | Interface to external GPU FET driver (e.g., TPS51601); support FCCM/SKIP mode selection and phase control |
| CVFB / GVFB | CPU/GPU voltage feedback inputs | Direct connection to VCORE/VGFX; soft-stop transistor integrated on CVFB for controlled shutdown |
| COCP-R / GOCP-R | CPU/GPU overcurrent threshold programming | Resistor-to-GND sets one of eight valley-current OCP levels (3.9–46.1 mV) and USR/OSR thresholds |
| SLEWA | Slew rate and SVID address selection | Resistor-to-GND selects base slew rate (1.25–26 mV/µs) and defines SVID slave address for TPS59650 variant |
| CTHERM / GTHERM | CPU/GPU thermal sensor inputs | NTC thermistor divider interfaces for IMVP-7 thermal bit reporting (bit0–bit7 = 755–430 mV thresholds) |
Key Features
| Feature | Design Value |
|---|---|
| Dual-channel IMVP-7 compliance | Fully implements Serial VID protocol, VR_ON, PGOOD, ALERT, VR_HOT, and thermal register mapping for both CPU and GPU rails |
| Integrated CPU gate drivers | Two 2.2-A sink/source drivers (CDH1/CDL1, CDH2/CDL2) eliminate need for external drivers in first two CPU phases |
| AutoBalance™ phase balancing | Internal current share tolerance ≤±3% ensures balanced load distribution across CPU phases without external circuitry |
| Programmable USR/OSR | Voltage-programmable thresholds (COCP-R/GOCP-R) reduce VCORE undershoot/overshoot during load transients by up to 40% |
| 8-level current limit selection | Resistor-programmed OCP thresholds (3.9–46.1 mV) allow precise current protection tuning per phase and channel |
| Thermal-aware soft-stop | CVFB-integrated discharge transistor enables controlled voltage ramp-down during VR_ON deassertion, preventing system reset glitches |
Applications
| Mobile Notebook VCORE | Ultrabook GPU Power |
|---|---|
Use Scenario: Dual-rail power delivery for Intel Core i-series processors and discrete GPUs in thin-and-light notebooks. IC Role / Device Role / Timing Role: Primary IMVP-7 VCORE controller managing CPU core voltage (3-phase) and GPU graphics voltage (2-phase) with synchronized SVID commands. Use Value: Enables single-chip solution for dual-domain power management, reducing BOM count and PCB area versus discrete controllers. |
Use Scenario: High-efficiency GPU rail in convertible laptops requiring dynamic voltage scaling during graphics-intensive workloads. IC Role / Device Role / Timing Role: GPU channel controller with SKIP/FCCM mode switching and thermal throttling via GTHERM feedback. Use Value: Achieves >90% efficiency at 20 A load (VIN=20 V) while supporting rapid VID transitions (<2 µs) for real-time GPU frequency scaling. |
| Gaming Laptop VRM | Embedded Mobile Platform |
Use Scenario: High-current VRM design for gaming laptops with multi-core CPUs and mid-tier dGPUs operating under sustained thermal load. IC Role / Device Role / Timing Role: Dual-channel controller with AutoBalance™ and thermal shutdown (155°C) protecting both CPU and GPU domains during overclocking events. Use Value: Delivers 94-A CPU peak current capability with <100-µs transient recovery (66-A step), minimizing voltage droop during burst workloads. |
Use Scenario: Ruggedized embedded systems (e.g., medical tablets, industrial HMIs) requiring extended temperature operation and long-term supply continuity. IC Role / Device Role / Timing Role: Industrial-grade power controller with –40°C to 105°C rating, IMVP-7 compatibility, and robust ESD protection (2-kV HBM). Use Value: Ensures stable VCORE/GPU voltage under wide ambient conditions and mechanical stress, validated per JEDEC JESD22 standards. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel IMVP-7 controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51650RSLR | Rated for –10°C to 105°C; no SVID address selection; identical pinout and feature set except SLEWA function | Targeted for consumer notebooks with narrower ambient range; lacks programmable SVID address for multi-controller systems | Select when industrial temperature range is not required and system uses single TPS5x650 instance |
| RT8803AZQW | Single-channel IMVP-7 controller (CPU only); requires external GPU controller; different pinout and no integrated GPU PWM outputs | Used in cost-sensitive designs where GPU rail is managed separately; lacks dual-channel coordination and shared thermal monitoring | Choose only if GPU power is handled by discrete IC or SoC-integrated regulator, not for integrated dual-rail solutions |
Compared with TPS59650RSLR, TPS51650RSLR offers identical performance but excludes SVID address programmability and industrial temperature range, while RT8803AZQW provides CPU-only control and requires additional components to replicate dual-rail functionality - making TPS59650RSLR the sole fit for compact, thermally robust, and address-configurable IMVP-7 dual-channel designs.
Availability
TPS59650RSLR is available at Aetrix Electronics and suitable for mobile computing, ultrabook platform development, and embedded industrial applications requiring stable component supply and long lifecycle support.
Supply support for TPS59650RSLR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies with over 50 years of innovation in high-reliability power conversion solutions.
The TPS59650 belongs to TI's IMVP-7-compliant VRM controller product line, engineered specifically for high-efficiency, low-noise dual-rail VCORE/GPU power delivery in space-constrained mobile platforms.
FAQ
What is the operating temperature range of the TPS59650RSLR?
The TPS59650RSLR is rated for operation from –40°C to 105°C ambient temperature, making it suitable for industrial and extended-temperature mobile applications. This exceeds the –10°C to 105°C range of the pin-compatible TPS51650RSLR and is validated per JEDEC JESD22 thermal testing standards.
How does the TPS59650RSLR implement IMVP-7 Serial VID communication?
The TPS59650RSLR implements full IMVP-7 SVID protocol via dedicated VCLK (1-V logic clock) and VDIO (1-V bidirectional data) pins, supporting SetVID, GetVID, Read/Write registers, and thermal bit reporting. Its SLEWA pin also sets the base SVID slave address, enabling multi-controller configurations on the same bus.
Can the TPS59650RSLR drive three CPU phases without external components?
No - the TPS59650RSLR integrates drivers for only two CPU phases (CDH1/CDL1 and CDH2/CDL2). A third phase requires an external FET driver such as the TPS51601, which is explicitly referenced in TI's documentation as the companion device for 3-phase CPU operation.
What protection features are built into the TPS59650RSLR?
The TPS59650RSLR includes overvoltage protection (OVP) and undervoltage protection (UVP) on CVFB/GVFB pins, thermal shutdown at 155°C with 20°C hysteresis, VR_HOT and ALERT open-drain fault signaling, soft-stop via CVFB discharge transistor, and programmable valley-current OCP with eight selectable thresholds per channel.
How is GPU phase control implemented in the TPS59650RSLR?
GPU phase control is implemented through GPWM1, GPWM2, and GSKIP outputs - 5-V logic-level signals that drive an external FET driver (e.g., TPS51601). GSKIP toggles between forced continuous conduction mode (FCCM) and skip mode, while GPWM1/GPWM2 provide independent phase timing control for 1- or 2-phase GPU operation.
TPS59650RSLR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- D-CAP+™
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Controller, Intel IMVP-7
- Voltage - Input:
- 3V ~ 28V
- Number of Outputs:
- 2
- Voltage - Output:
- 0.25V ~ 1.52V
- Operating Temperature:
- -40°C ~ 105°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-VQFN (6x6)
TPS59650RSLR FAQ
1.How can I place an order for TPS59650RSLR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS59650RSLR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS59650RSLR reliable?
The price and inventory of TPS59650RSLR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS59650RSLR is usually 5 days.
3.What payment methods are accepted for TPS59650RSLR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS59650RSLR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS59650RSLR?
TPS59650RSLR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS59650RSLR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS59650RSLR?
For technical support, including TPS59650RSLR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS59650RSLR requirements.
6.How does Aetrix verify that TPS59650RSLR is sourced from the original manufacturer or authorized distributors?
All TPS59650RSLR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS59650RSLR meets industry standards.
7.What is the process for return or replacement of TPS59650RSLR?
All TPS59650RSLR units undergo pre-shipment inspection (PSI). If there is an issue with TPS59650RSLR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS59650RSLR part is unused and in its original packaging.
Return procedure for TPS59650RSLR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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