My Inquiry
My Account
Texas Instruments TPS61130PW
- Part No.:
- TPS61130PW
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS61130PW.pdf
- Description:
- IC REG DL BUCK/BST/LNR 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:1,687
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS61130PW from Texas Instruments is a synchronous SEPIC and flyback DC-DC converter with integrated 200-mA reverse-voltage-protected LDO, designed for single-cell Li-Ion/Li-Polymer or multi-cell alkaline/NiMH battery-powered portable systems. It delivers up to 300 mA from the SEPIC stage (adjustable 2.5–5.5 V output) and supports dual-output regulation, with quiescent current as low as 10 µA and 400–600 kHz fixed-frequency PWM operation.
For engineers reviewing the TPS61130PW datasheet, TPS61130PW pinout, TPS61130PW application, or TPS61130PW equivalent, key selection considerations include its adjustable dual-output capability, low-battery detection interface (LBI/LBO), power-good signaling (PGOOD), thermal shutdown protection, and compatibility with compact 16-pin TSSOP packaging for space-constrained portable designs.
Technical Context
The TPS61130PW implements a fixed-frequency, multiple-feedforward PWM controller with synchronous rectification using integrated N-channel and P-channel MOSFETs-enabling up to 90% efficiency and eliminating external Schottky diodes. Its SEPIC topology provides true buck-boost behavior with no DC path between input and output, supporting input voltages both above and below regulated output levels.
Control logic includes independent enable/disable for the SEPIC stage (EN) and LDO stage (LDOEN), programmable low-battery detection (500 mV threshold with 10 mV hysteresis at LBI), and selectable Power Save mode (via SKIPEN) that maintains high light-load efficiency. The device integrates antiringing circuitry on SWP/SWN pins and features separate PGND and GND pins to minimize ground shift under high-current switching.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Topology | Synchronous SEPIC/flyback - enables true buck-boost operation without polarity inversion or external diode |
| SEPIC Output Current | Up to 300 mA - sufficient for powering core logic, display bias, or RF sections in portable devices |
| SEPIC Output Voltage | Adjustable 2.5–5.5 V via FB pin - supports common rails like 3.3 V, 5 V, or custom intermediate voltages |
| LDO Output Current | 200 mA typical - powers auxiliary circuits (e.g., sensors, audio codecs) with low-noise post-regulation |
| Quiescent Current | 10 µA typical into VBAT - extends battery life in standby or low-power monitoring modes |
| Switching Frequency | 400–600 kHz - balances EMI performance and inductor size; supports standard 22 µH magnetics |
| Input Voltage Range | 1.8–6.5 V - covers full discharge range of 1-cell Li-ion (2.5–4.2 V), 2–4-cell alkaline/NiMH (2.4–6.0 V) |
| Thermal Protection | 140°C trip with 20°C hysteresis - prevents latch-up during overload or poor PCB thermal design |
Pinout & Package
TPS61130PW is housed in a 16-pin TSSOP package (5.00 mm × 4.40 mm body size) with exposed thermal pad connected internally to PGND. The package supports tape-and-reel delivery (add R suffix: TPS61130PWR).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN (Pin 7) | SEPIC enable control | Active-high logic input; disables entire DC-DC stage and disconnects load from battery when low |
| FB (Pin 15) | SEPIC feedback node | Connects to resistor divider for precise adjustable output voltage regulation (reference = 500 mV) |
| VOUT (Pin 16) | SEPIC regulated output | Main power rail output; capable of sourcing up to 300 mA with ±3% total accuracy |
| LDOEN (Pin 8) | LDO enable control | Independent active-high enable for integrated LDO; logic referenced to LDOIN voltage |
| LDOOUT (Pin 10) | LDO regulated output | Second output rail (adjustable 0.9–5.5 V); reverse-voltage protected and back-bias capable |
| PGOOD (Pin 14) | Power-good status flag | Open-drain output asserting high when VOUT is within 90–95% of target - used for sequencing or fault reporting |
| LBI (Pin 5) | Low-battery comparator input | Monitors scaled battery voltage; triggers LBO when input drops below 500 mV (10 mV hysteresis) |
| SWP (Pin 1) / SWN (Pin 2) | SEPIC switch terminals | High-side PMOS (SWP) and low-side NMOS (SWN) connections; integrated antiringing clamp reduces EMI |
| PGND (Pin 3) | Power ground return | Separate return path for high-current switching nodes; must be tied to GND at single point near GND pin |
| GND (Pin 12) | Control/logic ground | Reference for all analog comparators, error amplifiers, and digital inputs (EN, SKIPEN, LDOEN) |
Key Features
| Feature | Design Value |
|---|---|
| Integrated LDO with reverse-voltage protection | 200-mA output with back-bias capability - allows seamless switchover between battery and USB/AC adapter sources |
| Programmable low-battery detection | 500-mV threshold with 10-mV hysteresis at LBI pin - enables customizable battery fuel-gauge alerts without external components |
| Power-Good (PGOOD) output | Open-drain signal with 30-µs delay - provides reliable system-level power sequencing for microcontrollers or FPGAs |
| Antiringing switch integration | Clamps SW node to VBAT during DCM - reduces radiated EMI and eliminates need for snubber networks |
| Independent enable controls | Separate EN (SEPIC) and LDOEN (LDO) pins - supports flexible power-state management and partial subsystem shutdown |
| Soft-start with current limiting | Start-up duty cycle begins at 50%; peak switch current limited to 40% nominal until regulation achieved - prevents battery inrush |
Applications
| Portable Audio Playback | USB-Powered Diagnostic Tool |
|---|---|
Use Scenario: MP3 player powered by single-cell Li-ion battery with dynamic load ranging from 10 mA (standby) to 250 mA (audio decode + OLED backlight). IC Role / Device Role / Timing Role: Primary DC-DC regulator generating 3.3 V for SoC and 1.8 V for display driver via LDOOUT; manages battery discharge profile and low-fuel warning. Use Value: Dual-output architecture eliminates need for second discrete regulator; 10 µA quiescent current extends playback time by >15% versus comparable solutions. |
Use Scenario: Handheld medical sensor interface drawing power from USB host (5 V) or internal coin cell during field use. IC Role / Device Role / Timing Role: Configured in dual-input mode: SEPIC stage disabled (EN = low), LDO powered from USB (LDOIN = 5 V) to generate 3.3 V; switches to battery when USB removed. Use Value: Reverse-voltage protected LDO enables automatic source switchover without external OR-ing FETs or diodes - reducing BOM count and board area. |
| Industrial Data Logger | Wireless Remote Control |
Use Scenario: Battery-operated environmental monitor sampling temperature/humidity every 30 seconds, transmitting via BLE during wake cycles. IC Role / Device Role / Timing Role: Supplies 3.3 V to MCU and radio; uses PGOOD to gate radio enable; LBI monitors battery health and triggers graceful shutdown at 2.8 V. Use Value: Integrated low-battery comparator and power-good output eliminate two external ICs - improving reliability and simplifying firmware power-state logic. |
Use Scenario: IR remote using two AAA alkaline cells (2.4–3.2 V range) powering 3.3 V MCU and IR LED driver with burst-mode transmission. IC Role / Device Role / Timing Role: SEPIC stage generates stable 3.3 V across full battery range; SKIPEN enables Power Save mode during 99% idle time to minimize leakage. Use Value: 400–600 kHz switching frequency allows use of small 22 µH inductors; 90% peak efficiency sustains >2-year battery life at typical duty cycle. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output DC-DC converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS61131PW | Fixed 3.3-V SEPIC output and fixed 3.3-V LDO output - no external feedback resistors required | Eliminates FB resistor network but lacks output flexibility; unsuitable for non-standard voltage rails | Select when system requires only 3.3 V on both outputs and board space is constrained |
| TPS61132PW | Fixed 3.3-V SEPIC output and fixed 1.5-V LDO output - optimized for low-voltage logic or sensor biasing | Provides dedicated low-voltage LDO rail; not configurable for higher LDO outputs like 2.5 V or 5 V | Select when secondary rail must be precisely 1.5 V (e.g., for specific analog sensor interfaces) |
Compared with TPS61131PW and TPS61132PW, the TPS61130PW offers full adjustability on both outputs - enabling support for diverse voltage combinations (e.g., 5 V + 2.5 V) without redesigning feedback networks or changing BOMs across product variants.
Availability
TPS61130PW is available at Aetrix Electronics and suitable for portable medical devices, USB-C peripheral power management, industrial data loggers, and battery-backed wireless sensors requiring stable component supply across extended production lifecycles.
Supply support for TPS61130PW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-efficiency DC-DC conversion for battery-powered systems.
The TPS6113x product line was engineered specifically for portable electronics requiring dual regulated outputs from single- or multi-cell batteries - emphasizing ultra-low quiescent current, integrated protection features, and minimal external component count.
FAQ
What is the maximum output current capability of the TPS61130PW's SEPIC stage?
The TPS61130PW's SEPIC stage delivers up to 300 mA continuous output current under typical conditions (e.g., VOUT = 3.3 V, VI = 1.8–3.6 V). Peak switch current is internally limited to 1300 mA (typical), and actual achievable current depends on input voltage, output voltage, ambient temperature, and PCB thermal design. Derating applies above 85°C ambient.
Can the TPS61130PW operate with input voltages below 1.8 V?
No - the TPS61130PW has a recommended minimum input voltage of 1.8 V and incorporates undervoltage lockout that disables operation if VBAT falls below approximately 1.6 V. Operation below 1.8 V is outside specification and may result in unstable regulation, failure to start, or undefined behavior. For sub-1.8 V battery chemistries, consider alternative architectures.
How does the LDO section of the TPS61130PW handle reverse current when powered from an external source?
The TPS61130PW's integrated LDO includes reverse-voltage protection that blocks current flow from LDOOUT back into LDOIN when LDOIN < LDOOUT. This allows safe back-biasing - for example, when an external 5 V USB supply powers the LDO while the SEPIC stage is disabled - preventing damage or battery drain through the LDO path.
Is the TPS61130PW pin-compatible with other members of the TPS6113x family?
Yes - the TPS61130PW shares identical pinout, package dimensions (16-pin TSSOP), and terminal functions with TPS61131PW and TPS61132PW. All three variants are mechanically and electrically interchangeable on PCBs; functional differences (fixed vs. adjustable outputs) are implemented internally and require no layout changes.
What external components are mandatory for basic TPS61130PW operation?
Mandatory external components for TPS61130PW include: two 22 µH coupled inductors (L1-A/L1-B), one 100 µF low-ESR output capacitor (C4), one 10 µF input capacitor (C3), two 2.2 µF ceramic capacitors (C5/C6) on VOUT and LDOOUT, plus FB and LDOSENSE resistor dividers for adjustable outputs. The thermal pad must be soldered to PGND for thermal performance.
TPS61130PW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Topology:
- Step-Down/Step-Up (Buck/Boost) (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 500kHz
- Voltage/Current - Output 1:
- 2.5V ~ 5.5V, 300mA
- Voltage/Current - Output 2:
- 2.5V ~ 5.5V, 320mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
TPS61130PW FAQ
1.How can I place an order for TPS61130PW through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS61130PW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS61130PW reliable?
The price and inventory of TPS61130PW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS61130PW is usually 5 days.
3.What payment methods are accepted for TPS61130PW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS61130PW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS61130PW?
TPS61130PW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS61130PW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS61130PW?
For technical support, including TPS61130PW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS61130PW requirements.
6.How does Aetrix verify that TPS61130PW is sourced from the original manufacturer or authorized distributors?
All TPS61130PW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS61130PW meets industry standards.
7.What is the process for return or replacement of TPS61130PW?
All TPS61130PW units undergo pre-shipment inspection (PSI). If there is an issue with TPS61130PW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS61130PW part is unused and in its original packaging.
Return procedure for TPS61130PW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS61130PW Tags
-
TPS6521905RHBR
Texas Instruments
-
MIC3385YHL-TR
Microchip Technology
-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments
-
A4402KLPTR-T
Allegro MicroSystems
-
BD71847AMWV-E2
ROHM Semiconductor
-
ADP5040ACPZ-1-R7
Analog Devices Inc.
-
LT3048IDC#TRPBF
Analog Devices Inc.
-
ADP5037ACPZ-R7
Analog Devices Inc.
-
XRP7714ILB-F
MaxLinear, Inc.
-
LTC3260EDE#TRPBF
Analog Devices Inc.
-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
