Texas Instruments TPS61130PWR
- Part No.:
- TPS61130PWR
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS61130PWR.pdf
- Description:
- IC REG DL BUCK/BST/LNR 16TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,574
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Product details
Overview
TPS61130PWR from Texas Instruments is a synchronous SEPIC and flyback DC-DC converter with integrated 200-mA reverse-voltage-protected LDO, designed for single-cell Li-Ion/Li-Polymer or multi-cell alkaline/NiMH battery-powered systems. It delivers up to 300 mA from the SEPIC stage (adjustable 2.5–5.5 V output) and supports dual-output operation with independent LDO enable control, used in portable audio players, PDAs, and USB-powered devices.
For engineers reviewing the TPS61130PWR datasheet, TPS61130PWR pinout, TPS61130PWR application, or TPS61130PWR equivalent, key selection considerations include its 1.8–6.5 V input range, 500 kHz fixed-frequency PWM operation, 40 µA typical quiescent current, power-good signaling, low-battery detection interface, and thermal-pad-equipped TSSOP-16 package compatibility.
Technical Context
The TPS61130PWR implements a fixed-frequency, multiple-feedforward PWM controller with synchronous rectification using integrated N-channel and P-channel MOSFETs. Its SEPIC topology enables buck-boost conversion without DC path between input and output, supporting input voltages both above and below regulated output levels.
It integrates a dedicated LDO stage with reverse-voltage protection, independently enabled via LDOEN, and features programmable low-battery detection (500 mV threshold at LBI), antiringing switch for EMI reduction, and overtemperature shutdown at 140°C. Power save mode (via SKIPEN) dynamically disables switching at light loads to maintain high efficiency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 1.8 V to 6.5 V - supports single-cell Li-ion (2.5–4.2 V), two-to-four-cell alkaline/NiMH (1.8–6.5 V) |
| SEPIC Output Range | Adjustable 2.5 V to 5.5 V - set via external FB resistor divider; ±3% total accuracy including line/load regulation |
| LDO Output Range | Adjustable 0.9 V to 5.5 V - configured via LDOSENSE feedback; 300 mV dropout at 200 mA |
| Switching Frequency | 400–600 kHz (typ. 500 kHz) - fixed-frequency PWM with optional power-save mode for light-load efficiency |
| Peak Switch Current Limit | 1100–1600 mA - protects internal SWP/SWN MOSFETs and external inductors during overload or short-circuit |
| Quiescent Current | 10–25 µA (DC-DC active) - enables >90% efficiency at moderate loads and ultra-low standby drain |
| Thermal Resistance (RθJA) | 100.5 °C/W - measured in TSSOP-16 package; requires thermal pad soldering to PGND for safe 125°C junction operation |
Pinout & Package
TSSOP-16 package (5.00 mm × 4.40 mm), thermally enhanced with exposed thermal pad connected to PGND. Pin numbering follows standard TSSOP top-view orientation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SWP (Pin 1) | SEPIC rectifying switch input | Connects to source of internal PMOS; clamped to VBAT during antiringing operation |
| SWN (Pin 2) | SEPIC main switch input | Drain of internal NMOS; requires low-inductance PGND return path |
| PGND (Pin 3) | Power ground | Return for high-current SEPIC switches; must be isolated from logic GND except at single-point connection |
| VBAT (Pin 4) | Main supply input | Accepts 1.8–6.5 V battery or adapter input; includes undervoltage lockout (~1.6 V) |
| LBI (Pin 5) | Low-battery comparator input | Monitors scaled battery voltage; 500 mV threshold with 10 mV hysteresis; active only when EN = high |
| SKIPEN (Pin 6) | Power-save mode enable | High = enable pulse-skipping at light load; low = forced fixed-frequency operation |
| EN (Pin 7) | DC-DC enable input | Active-high logic; disables all switching, disconnects battery via backgate control, reduces shutdown current to 0.2–1 µA |
| LDOEN (Pin 8) | LDO enable input | Independent enable for LDO stage; logic thresholds referenced to LDOIN voltage |
| LDOIN (Pin 9) | LDO input supply | Accepts 1.8–7 V; can be tied to VBAT, VOUT, or external rail; reverse-current protected |
| LDOOUT (Pin 10) | LDO regulated output | Delivers up to 320 mA; fixed or adjustable via LDOSENSE; includes power-good monitoring capability |
| LDOSENSE (Pin 11) | LDO feedback input | Connects to resistor divider for adjustable LDO output; tied to LDOOUT for fixed-voltage versions |
| GND (Pin 12) | Logic/control ground | Reference for EN, SKIPEN, LDOEN, FB, PGOOD, LBO; separate from PGND to avoid noise coupling |
| LBO (Pin 13) | Low-battery open-drain output | Active-low flag; requires external pull-up; high-impedance when device is disabled |
| PGOOD (Pin 14) | SEPIC power-good indicator | Open-drain output asserting when VOUT is within ±8% of target; used to sequence downstream rails or processors |
| FB (Pin 15) | SEPIC feedback input | Sets adjustable VOUT via resistor divider to internal 500 mV reference; ±3% regulation accuracy |
| VOUT (Pin 16) | SEPIC regulated output | Delivers up to 300 mA; connects to output capacitor and LDOIN for dual-rail configurations |
Key Features
| Feature | Design Value |
|---|---|
| Synchronous SEPIC/Flyback topology | Enables true buck-boost operation with no DC path from input to output - eliminates need for external isolation components |
| Integrated 200-mA reverse-protected LDO | Provides second regulated rail with independent enable (LDOEN), programmable output (0.9–5.5 V), and back-bias tolerance |
| Antiringing switch | Clamps SW node to VBAT during discontinuous conduction mode - reduces radiated EMI without external snubbers |
| Programmable low-battery detection | 500 mV LBI threshold with 10 mV hysteresis - configurable via external resistor divider for precise battery end-of-life signaling |
| Thermal shutdown with hysteresis | Triggers at 140°C junction temperature and releases at 120°C - prevents damage during sustained overload or poor PCB thermal design |
| Load disconnect during shutdown | Backgate diode of high-side PMOS is actively turned off when EN = low - ensures complete battery isolation and zero load current |
Applications
| Portable Audio Players | PDAs and Handheld Terminals |
|---|---|
Use Scenario: MP3 player powered by single-cell Li-ion battery (2.5–4.2 V) requiring stable 3.3 V for digital signal processor and 1.5 V for memory interface. IC Role / Device Role / Timing Role: TPS61130PWR acts as primary buck-boost regulator generating 3.3 V from varying battery voltage, while its integrated LDO supplies clean 1.5 V rail derived from VOUT. Use Value: Eliminates need for separate LDO IC and reduces BOM count; 40 µA quiescent current extends playback time during pause states. |
Use Scenario: Industrial PDA operating from dual alkaline cells (2.4–3.2 V) needing 3.3 V for microcontroller and 2.8 V for display driver, with battery health monitoring. IC Role / Device Role / Timing Role: TPS61130PWR provides regulated 3.3 V output and uses LDO to generate 2.8 V; LBI/LBO pins implement user-alert battery warning at 2.6 V. Use Value: Single-chip dual-output solution avoids cross-regulation issues; programmable LBI threshold enables precise end-of-life detection across battery chemistries. |
| USB-Powered Portable Instruments | Dual-Input Medical Sensors |
Use Scenario: Handheld diagnostic tool powered either by USB (5 V) or internal Li-Po (3.0–4.2 V), requiring consistent 3.3 V and 1.8 V outputs regardless of source. IC Role / Device Role / Timing Role: TPS61130PWR's LDOIN accepts either VOUT or direct USB input; LDO generates 1.8 V while SEPIC maintains 3.3 V - enabling seamless source switchover. Use Value: Reverse-voltage protected LDO allows safe back-powering from USB without risk of battery discharge; PGOOD enables controlled system boot sequencing. |
Use Scenario: Wearable biosensor using coin-cell (3 V) for low-power analog front-end and Li-ion (3.3–4.2 V) for digital processing, requiring isolated 2.5 V and 3.3 V rails. IC Role / Device Role / Timing Role: TPS61130PWR SEPIC stage powers digital subsystem from Li-ion; LDOIN supplied from coin-cell generates 2.5 V analog rail - eliminating cross-talk between power domains. Use Value: Independent enable (EN/LDOEN) and shutdown isolation prevent leakage paths; dual-ground architecture minimizes noise coupling into sensitive analog circuits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output buck-boost regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS61088RHLR | Higher 3.5-A switch current, fixed 5-V output, no integrated LDO, QFN-16 package | Single-output high-current boost only; lacks dual-rail capability and battery supervision features | Select when >300 mA output or fixed 5 V is required; not suitable for LDO-dependent dual-rail designs |
| MAX17222ETA+ | 1.2-A boost-only converter, 0.9-μA quiescent current, no LDO, no battery monitor, 6-pin WLP | Ultra-low IQ for energy harvesting; no dual output, no PGOOD, no thermal protection | Choose for minimal footprint and lowest standby drain where dual rail and safety features are unnecessary |
Compared with TPS61130PWR, TPS61088RHLR offers higher output current but omits the integrated LDO and battery monitoring, while MAX17222ETA+ achieves ultra-low quiescent current at the cost of missing critical system-level functions like power good signaling and thermal protection - making TPS61130PWR uniquely suited for compact, battery-supervised dual-rail portable systems.
Availability
TPS61130PWR is available at Aetrix Electronics and suitable for portable audio players, handheld terminals, USB-powered instruments, medical sensors, and battery-backed industrial controllers requiring stable component supply across long production lifecycles.
Supply support for TPS61130PWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions, with decades of expertise in battery-powered system power architecture.
The TPS6113x product line was engineered specifically for portable electronics requiring efficient dual-output regulation from variable-input batteries - combining SEPIC conversion, integrated LDO, and intelligent supervision in a thermally optimized package.
FAQ
What is the function of the SKIPEN pin on the TPS61130PWR?
The SKIPEN pin on the TPS61130PWR controls power-save mode operation. When pulled high, it enables pulse-skipping at light loads to maintain high efficiency; when grounded, the TPS61130PWR operates in forced continuous conduction mode at fixed 500 kHz. This pin directly affects dynamic efficiency behavior but does not alter output voltage regulation or enable/disable functionality - those remain controlled by EN and LDOEN respectively.
Can the TPS61130PWR generate two independent output voltages simultaneously?
Yes, the TPS61130PWR can generate two independent regulated outputs simultaneously: the primary SEPIC output (VOUT, adjustable 2.5–5.5 V) and a secondary LDO output (LDOOUT, adjustable 0.9–5.5 V). The LDO can be powered from VOUT, VBAT, or an external rail, and is enabled independently via LDOEN. Both outputs operate concurrently with separate feedback paths (FB and LDOSENSE), allowing distinct voltage levels and load conditions without cross-regulation.
How does the TPS61130PWR achieve battery disconnection during shutdown?
The TPS61130PWR achieves full battery disconnection during shutdown by actively turning off the backgate diode of the internal high-side PMOS rectifier when EN is low. Unlike passive diode-based isolation, this circuit disconnects the cathode of the backgate diode from its source, eliminating reverse current paths. As a result, the TPS61130PWR draws only 0.2–1 µA shutdown current and fully isolates the battery from VOUT, LDOOUT, and all internal circuitry - critical for long-term storage in battery-powered devices.
What is the purpose of the separate GND and PGND pins on the TPS61130PWR?
The TPS61130PWR uses separate GND (Pin 12) and PGND (Pin 3) pins to isolate high-current power return paths from sensitive control circuitry. PGND carries peak SEPIC switch currents (up to 1.6 A), while GND serves as the reference for EN, SKIPEN, FB, PGOOD, and LBO signals. This separation prevents ground bounce and noise coupling into regulation and monitoring functions. Both grounds must connect to the PCB ground plane at a single point near the GND pin to maintain signal integrity and thermal performance.
Is the TPS61130PWR compatible with ceramic output capacitors?
Yes, the TPS61130PWR is fully compatible with ceramic output capacitors. Its control loop and antiringing circuit are designed for low-ESR ceramic types - typical designs use 10 µF at VOUT and 2.2 µF at LDOOUT. Ceramic capacitors improve transient response and reduce board area versus tantalum alternatives. However, input capacitance (C4 in datasheet Figure 15) should retain a low-ESR tantalum or polymer type in parallel with ceramics to handle high RMS input ripple current without derating.
TPS61130PWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down/Step-Up (Buck/Boost) (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 500kHz
- Voltage/Current - Output 1:
- 2.5V ~ 5.5V, 300mA
- Voltage/Current - Output 2:
- 2.5V ~ 5.5V, 320mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
TPS61130PWR FAQ
1.How can I place an order for TPS61130PWR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS61130PWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS61130PWR reliable?
The price and inventory of TPS61130PWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS61130PWR is usually 5 days.
3.What payment methods are accepted for TPS61130PWR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS61130PWR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS61130PWR?
TPS61130PWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS61130PWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS61130PWR?
For technical support, including TPS61130PWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS61130PWR requirements.
6.How does Aetrix verify that TPS61130PWR is sourced from the original manufacturer or authorized distributors?
All TPS61130PWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS61130PWR meets industry standards.
7.What is the process for return or replacement of TPS61130PWR?
All TPS61130PWR units undergo pre-shipment inspection (PSI). If there is an issue with TPS61130PWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS61130PWR part is unused and in its original packaging.
Return procedure for TPS61130PWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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