My Inquiry
My Account
Texas Instruments TPS61130PWRG4
- Part No.:
- TPS61130PWRG4
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
TPS61130PWRG4.pdf
- Description:
- IC REG DL BUCK/BST/LNR 16TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,220
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS61130PWRG4 from Texas Instruments is a synchronous SEPIC and flyback DC-DC converter with integrated 200-mA reverse-voltage-protected LDO, designed for dual-output portable power systems. It delivers up to 300 mA from the SEPIC stage (adjustable 2.5–5.5 V) and supports post-regulated or independent LDO output (adjustable 0.9–5.5 V), operating from 1.8–6.5 V input - ideal for single-cell Li-ion, multi-cell alkaline/NiMH battery-powered MP3 players, PDAs, and USB-powered portable equipment.
For engineers reviewing the TPS61130PWRG4 datasheet, TPS61130PWRG4 pinout, TPS61130PWRG4 application, or TPS61130PWRG4 equivalent, key selection criteria include its dual-output architecture (SEPIC + LDO), 500-kHz fixed-frequency PWM with power-save mode, 40-μA quiescent current, low-battery detection (LBI/LBO), and PGOOD signaling - all in a thermally enhanced 16-pin TSSOP package.
Technical Context
The TPS61130PWRG4 implements a fixed-frequency, synchronous SEPIC topology with NMOS/PNOS switches (RDS(on) = 200 mΩ / 250 mΩ), peak switch current limit of 1300 mA (typ), and integrated antiringing circuitry to suppress SW-node oscillation in discontinuous conduction mode. Its control loop uses feedforward compensation with internal 500-mV reference and error amplifier feedback via FB pin.
The device integrates a separate, independently enabled LDO stage with 300-mV dropout at 200 mA, ±3% total output accuracy, and reverse-voltage protection. Low-battery detection (500-mV threshold, 10-mV hysteresis on LBI) and thermal shutdown (140°C, 20°C hysteresis) operate only when EN is high, and both grounds (GND and PGND) require single-point PCB connection near GND for stability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 1.8 V to 6.5 V - supports single-cell Li-ion (2.5–4.2 V), dual/triple alkaline/NiMH (1.8–5.5 V), and USB 5-V input without external regulation. |
| SEPIC Output Current | Up to 300 mA - sufficient for powering 3.3-V microcontrollers, displays, or RF modules from variable battery sources. |
| SEPIC Output Voltage | Adjustable 2.5 V to 5.5 V - set via external resistor divider on FB pin; enables flexible rail generation across diverse loads. |
| LDO Output Current | 200 mA (max) - delivers stable second output with 300-mV dropout at full load, suitable for noise-sensitive analog or logic rails. |
| Quiescent Current | 40 μA (typ) - minimizes standby drain in battery-critical applications like always-on sensors or backup systems. |
| Switching Frequency | 500 kHz (typ) - balances inductor size (22 μH typical) and efficiency; supports power-save mode via SKIPEN for light-load optimization. |
| Protection Features | Overtemperature shutdown (140°C), undervoltage lockout (~1.6 V), soft-start, load disconnect during shutdown, and reverse-voltage protected LDO. |
Pinout & Package
TPS61130PWRG4 is housed in a 16-pin TSSOP package (5.00 mm × 4.40 mm) with exposed thermal pad connected to PGND for enhanced thermal performance. Pin functions are validated per TI SLVS431C datasheet Rev. C (September 2015).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN (Pin 7) | DC-DC enable input | Active-high logic: ties VBAT to enable SEPIC operation; pulls to GND for complete battery disconnect and <1-μA shutdown current. |
| FB (Pin 15) | SEPIC voltage feedback | Connects to resistor divider from VOUT to set adjustable output; referenced to internal 500-mV bandgap for ±3% regulation accuracy. |
| LDOEN (Pin 8) | LDO enable input | Independent active-high control for LDO stage; logic levels referenced to LDOIN, enabling use with external supplies (e.g., USB). |
| PGOOD (Pin 14) | Power-good indicator | Open-drain output asserting high when VOUT is within 92%–95% of target - used to sequence downstream regulators or wake microcontrollers. |
| LBI / LBO (Pins 5 / 13) | Low-battery monitor I/O | LBI accepts scaled battery voltage; LBO asserts open-drain low when LBI falls below 500 mV (10-mV hysteresis) - enables system-level battery management. |
| SWP / SWN (Pins 1 / 2) | SEPIC switch terminals | SWP connects to rectifying PMOS source; SWN to NMOS source - requires careful layout with PGND plane and minimized loop area for EMI control. |
| VOUT / LDOOUT (Pins 16 / 10) | Regulated outputs | VOUT = main SEPIC output; LDOOUT = post-regulated or alternate-source output - both support back-biasing and can be tied together with proper sequencing. |
| GND / PGND (Pins 12 / 3) | Signal / power ground | GND references all logic/control circuits; PGND carries high-switching currents - must connect at single point near GND pin to avoid noise coupling. |
Key Features
| Feature | Design Value |
|---|---|
| Synchronous SEPIC + integrated LDO | Enables dual regulated outputs from one IC: primary buck-boost rail (e.g., 3.3 V) and secondary low-noise rail (e.g., 1.8 V) - reduces BOM count and board space vs discrete solutions. |
| 40-μA quiescent current | Extends battery runtime in standby modes for portable devices requiring long shelf life or infrequent wake-up cycles. |
| Integrated antiringing switch | Clamps SW-node ringing during DCM, reducing radiated EMI without external snubbers - simplifies compliance testing for Class B emissions. |
| Independent LDO enable (LDOEN) | Allows LDO to remain active even when SEPIC is disabled (e.g., during USB charging), enabling seamless power-source handoff without system reset. |
| Load disconnect during shutdown | Breaks DC path from VBAT to VOUT and LDOOUT via backgate control - prevents battery drain and ensures true zero-current off-state. |
Applications
| MP3 Player Power Management | PDA Dual-Rail Supply |
|---|---|
|
Use Scenario: Portable audio player powered by single-cell Li-ion battery (2.5–4.2 V) requiring stable 3.3-V MCU core and 1.8-V codec supply. IC Role / Device Role / Timing Role: TPS61130PWRG4 generates 3.3 V via SEPIC stage and regulates 1.8 V via LDO - both rails track battery voltage drop while maintaining regulation down to 1.8 V input. Use Value: Eliminates need for separate boost + LDO ICs; 90% peak efficiency and 40-μA quiescent current extend playback time by >15% versus non-synchronous alternatives. |
Use Scenario: Handheld PDA with ARM processor (3.3 V), touchscreen controller (2.8 V), and SD card interface (3.3 V), powered by dual alkaline cells (1.8–3.2 V). IC Role / Device Role / Timing Role: TPS61130PWRG4 delivers 3.3 V from SEPIC and 2.8 V from LDO (via external resistor divider on LDOSENSE); PGOOD sequences processor boot after stable rails. Use Value: Single-chip dual-output solution reduces footprint by 40% vs discrete regulators; LDO's 60-dB PSRR at 100 kHz suppresses switching noise on analog rails. |
| USB-Powered Diagnostic Tool | Industrial Handheld Scanner |
|
Use Scenario: Battery-backed field diagnostic tool that operates from USB (5 V) or internal Li-ion (3.7 V nominal), needing 3.3-V logic and 5.0-V sensor bias. IC Role / Device Role / Timing Role: TPS61130PWRG4 uses USB as LDOIN to generate 5.0 V on LDOOUT while SEPIC remains disabled; when on battery, SEPIC powers both rails. Use Value: Seamless source transition without rail collapse; reverse-voltage protection prevents backfeed from USB to battery during charging. |
Use Scenario: Ruggedized barcode scanner with laser diode driver (5 V), CMOS imager (2.8 V), and BLE radio (3.3 V), powered by replaceable NiMH pack (2.4–4.0 V). IC Role / Device Role / Timing Role: TPS61130PWRG4 provides 5.0 V (SEPIC) and 2.8 V (LDO); LBI monitors pack voltage and triggers LBO alert before deep discharge. Use Value: Integrated low-battery comparator replaces external supervisor IC; thermal shutdown (140°C) ensures reliability in sealed enclosures with limited airflow. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output DC-DC converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS61131PW | Fixed 3.3-V SEPIC output and fixed 3.3-V LDO output - no FB or LDOSENSE pins required; identical pinout and package. | Eliminates external resistors but lacks output flexibility; unsuitable where adjustable rails or mixed voltages (e.g., 1.8 V + 3.3 V) are needed. | Select TPS61131PW only if both outputs are fixed at 3.3 V and BOM simplification outweighs design flexibility. |
| TPS61088RHLR | Single-output 2.5–5.5-V boost converter (10-A switch), no integrated LDO; requires external LDO for second rail. | Higher output current (up to 4 A) but increases component count, layout complexity, and cost for dual-rail systems. | Choose TPS61088RHLR only when >300 mA SEPIC current is required and separate LDO integration is acceptable. |
Compared with TPS61131PW, TPS61130PWRG4 offers full adjustability for both outputs at the cost of two external resistors; compared with TPS61088RHLR, it trades peak current capability for integrated dual-rail simplicity and lower quiescent current - making it optimal for compact, battery-constrained portable designs.
Availability
TPS61130PWRG4 is available at Aetrix Electronics and suitable for portable medical monitors, handheld test equipment, and USB-C peripheral power management requiring stable component supply, long-lifecycle support, and consistent parametric performance across production batches.
Supply support for TPS61130PWRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC-DC conversion and battery-powered system solutions.
The TPS6113x product line was engineered specifically for dual-output portable power applications - combining SEPIC topology efficiency with integrated LDO flexibility to eliminate discrete regulator combinations in space- and battery-life-constrained devices.
FAQ
What is the function of the SKIPEN pin on the TPS61130PWRG4?
The SKIPEN pin on the TPS61130PWRG4 enables or disables power-save mode: when pulled high, the device enters pulse-skipping mode at light loads to maintain high efficiency (e.g., >85% at 1-mA output); when grounded, it forces fixed 500-kHz PWM operation. This pin does not affect startup behavior or protection features - the TPS61130PWRG4 remains fully functional in either mode, with identical regulation accuracy and transient response.
Can the TPS61130PWRG4 generate two different output voltages simultaneously?
Yes, the TPS61130PWRG4 simultaneously delivers two independent regulated outputs: the SEPIC stage provides an adjustable 2.5–5.5-V rail (e.g., 3.3 V for digital logic), while the integrated LDO supplies a separately adjustable 0.9–5.5-V rail (e.g., 1.8 V for analog circuitry). Both outputs operate concurrently, with LDOEN and EN pins allowing independent enable/disable control - enabling the TPS61130PWRG4 to power heterogeneous subsystems from a single IC.
How does the low-battery detection work on the TPS61130PWRG4?
The TPS61130PWRG4 implements low-battery detection via the LBI pin, which compares a scaled-down battery voltage against an internal 500-mV threshold (with 10-mV hysteresis). When LBI drops below threshold, the open-drain LBO pin pulls low - signaling battery depletion to a host microcontroller. This circuit is only active when EN is high; during shutdown, LBO goes high-impedance. The TPS61130PWRG4 requires no external comparator or reference, reducing component count versus discrete supervision solutions.
What thermal considerations apply to the TPS61130PWRG4 in TSSOP package?
The TPS61130PWRG4 in TSSOP-16 (PW) package has a junction-to-ambient thermal resistance (RθJA) of 100.5°C/W under standard JEDEC conditions. To maintain safe operation up to 85°C ambient, the PCB must include adequate copper pour connected to the exposed thermal pad (Pin 16), routed to PGND. Derating is required above 60°C ambient - for example, at 85°C, maximum continuous output current drops to ~220 mA (SEPIC) and ~160 mA (LDO) per TI SLVS431C thermal data. The TPS61130PWRG4 includes overtemperature shutdown at 140°C with 20°C hysteresis.
Is the TPS61130PWRG4 compatible with ceramic output capacitors?
Yes, the TPS61130PWRG4 is fully compatible with ceramic output capacitors - the datasheet specifies 100-μF low-ESR tantalum for VOUT and 2.2-μF X7R/X5R ceramics for LDOOUT, but ceramic types meeting voltage rating, capacitance, and ESR requirements (e.g., ≤10 mΩ) are recommended for reduced size and improved reliability. Ceramic caps require careful attention to DC bias derating; for example, a 100-μF 6.3-V X5R capacitor may deliver only ~40 μF at 3.3-V bias - so parallel staging or higher-rated dielectrics are advised for critical hold-up applications.
TPS61130PWRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Topology:
- Step-Down/Step-Up (Buck/Boost) (1), Linear (LDO) (1)
- Number of Outputs:
- 2
- Frequency - Switching:
- 500kHz
- Voltage/Current - Output 1:
- 2.5V ~ 5.5V, 300mA
- Voltage/Current - Output 2:
- 2.5V ~ 5.5V, 320mA
- Voltage/Current - Output 3:
- -
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
TPS61130PWRG4 FAQ
1.How can I place an order for TPS61130PWRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS61130PWRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS61130PWRG4 reliable?
The price and inventory of TPS61130PWRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS61130PWRG4 is usually 5 days.
3.What payment methods are accepted for TPS61130PWRG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS61130PWRG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS61130PWRG4?
TPS61130PWRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS61130PWRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS61130PWRG4?
For technical support, including TPS61130PWRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS61130PWRG4 requirements.
6.How does Aetrix verify that TPS61130PWRG4 is sourced from the original manufacturer or authorized distributors?
All TPS61130PWRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS61130PWRG4 meets industry standards.
7.What is the process for return or replacement of TPS61130PWRG4?
All TPS61130PWRG4 units undergo pre-shipment inspection (PSI). If there is an issue with TPS61130PWRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS61130PWRG4 part is unused and in its original packaging.
Return procedure for TPS61130PWRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS61130PWRG4 Tags
-
TPS6521905RHBR
Texas Instruments
-
MIC3385YHL-TR
Microchip Technology
-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments
-
A4402KLPTR-T
Allegro MicroSystems
-
BD71847AMWV-E2
ROHM Semiconductor
-
ADP5040ACPZ-1-R7
Analog Devices Inc.
-
LT3048IDC#TRPBF
Analog Devices Inc.
-
ADP5037ACPZ-R7
Analog Devices Inc.
-
XRP7714ILB-F
MaxLinear, Inc.
-
LTC3260EDE#TRPBF
Analog Devices Inc.
-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
