Texas Instruments TPS61280EYFFR
- Part No.:
- TPS61280EYFFR
- Manufacturer:
- Texas Instruments
- Package:
- 16-UFBGA, DSBGA
- Datasheet:
-
TPS61280EYFFR.pdf
- Description:
- IC REG BOOST PROG 4A 16DSBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS61280EYFFR from Texas Instruments is a low-quiescent-current, wide-input-voltage DC/DC battery front-end converter optimized for single-cell Li-ion, Ni-rich, and silicon-anode batteries in smartphones and tablets. It delivers ≥4-A peak output at 3.35 V with 2.3-MHz synchronous boost operation, integrated 35-mΩ pass-through path, and programmable valley current limit up to 5 A.
For engineers reviewing the TPS61280EYFFR datasheet, TPS61280EYFFR pinout, TPS61280EYFFR application, or TPS61280EYFFR equivalent, this device supports I²C interface (up to 3.4 Mbps), in-situ E²PROM customization, true shutdown pass-through mode (3-µA IQ), and seamless transition between boost and bypass modes under dynamic load and battery voltage conditions.
Technical Context
The TPS61280EYFFR implements a synchronous boost architecture with dual-mode operation: high-efficiency pass-through (35 mΩ RDS(on)) when input voltage meets or exceeds the programmable threshold (3.4 V / 3.45 V), and 2.3-MHz PWM/PFM boost otherwise. Its valley current limit is factory-set to 5 A, and it features dedicated GPIO for mode selection (not fault/reset).
It integrates analog ground (AGND) and power ground (PGND) separation, thermal shutdown (140–160°C), and supports 1.2-V I/O logic levels-distinguishing it from the TPS61280D. The device uses internal E²PROM for configuration storage with write protection and operates across –40°C to +125°C junction temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 2.3 V to 4.85 V - supports full discharge of modern Li-ion, Ni-rich, and Si-anode cells without premature system cutoff. |
| IOUT Peak | ≥4 A at VOUT = 3.35 V, VIN ≥ 2.65 V - sustains high-pulse loads (e.g., RF transmitters) even from deeply discharged batteries. |
| Quiescent Current | 3 µA in shutdown (true pass-through), 25.6 µA typical in auto-bypass - maximizes shelf life and standby runtime. |
| Switching Frequency | 2.3 MHz fixed - enables use of ultra-small 470-nH inductors and <20 mm² total solution size. |
| Valley Current Limit | 5 A (TPS61280E-specific) - higher than TPS61280D's 3 A, enabling robust handling of transient surges in premium mobile platforms. |
| I²C Speed | Up to 3.4 Mbps (High-Speed mode) - allows rapid reconfiguration during system boot or mode switching without bus contention. |
| Pass-through RDS(on) | 35 mΩ (typical) - minimizes conduction loss and heat generation during direct battery-to-system delivery. |
Pinout & Package
TPS61280EYFFR is housed in a 16-bump DSBGA (YFF) package measuring 1.66 mm × 1.66 mm with 0.4-mm pitch. The package features separate AGND and PGND connections, dual VIN and VOUT pads for low-impedance routing, and bottom-side thermal pad (PGND-connected) for enhanced thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (A3, A4) | Input power supply | Dual-pad connection reduces trace resistance and inductance for high-pulse-current battery input. |
| VOUT (B3, B4) | Regulated output | Dual-pad layout supports high-current delivery to SoC or PMIC rails with minimal IR drop. |
| EN (A1) | Enable control | Active-high logic; rising edge resets registers and initiates startup sequence with pre-charge phase. |
| GPIO (A2) | Mode selection input | TPS61280E default: logic input to force PWM-only (low-noise) or PFM/PWM (efficiency-optimized) operation. |
| VSEL (B1) | Output voltage select | Configures boost/bypass threshold: 3.4 V (VSEL = L) or 3.45 V (VSEL = H) - sets system minimum operating voltage. |
| nBYP (C1) | Forced bypass control | Logic-low forces immediate pass-through mode regardless of VIN/VOUT relationship - used for fast system wake-up. |
| SCL/SDA (B2/C2) | I²C interface | Supports 3.4 Mbps HS-mode; SDA is open-drain, requires external pull-up; compatible with 1.2-V I/O systems. |
| SW (C3, C4) | Power switch node | Connects to inductor; dual-pad design lowers parasitic inductance and improves EMI performance. |
| PGND (D2–D4) | Power ground return | Three dedicated pads minimize ground bounce during high di/dt switching events. |
| AGND (D1) | Analog reference ground | Isolated from PGND to prevent noise coupling into feedback and regulation circuitry. |
Key Features
| Feature | Design Value |
|---|---|
| True shutdown pass-through | 3-µA quiescent current with battery directly connected to output - extends shelf life without external load switches. |
| In-situ E²PROM programming | User-configurable settings (VOUT, current limit, mode) stored on-chip with hardware write protection - eliminates need for external configuration EEPROM. |
| Dynamic mode transition | Seamless, automatic switching between boost and bypass based on real-time VIN/VOUT comparison - maintains stable system rail during battery sag. |
| Low-noise PWM mode | GPIO-driven forced PWM operation suppresses frequency variation - critical for noise-sensitive RF and audio subsystems. |
| Thermal-aware protection | 140–160°C thermal shutdown with hysteresis - prevents damage during sustained overload while allowing recovery after cooling. |
Applications
| Smartphone Power Management | Tablet PC Battery Interface |
|---|---|
|
Use Scenario: High-pulse RF transmission in LTE/5G bands causes instantaneous current spikes >3 A, collapsing weak battery voltage. IC Role / Device Role / Timing Role: Front-end pre-regulator that buffers battery voltage, supplies clean 3.35-V rail, and transitions between boost/bypass within microseconds. Use Value: Prevents system brownout and modem reset by delivering ≥4-A peak current from batteries as low as 2.65 V. |
Use Scenario: Dual-display tablet with discrete GPU requiring stable 3.35-V supply during burst rendering workloads. IC Role / Device Role / Timing Role: High-efficiency battery front-end managing input current limiting, voltage regulation, and thermal headroom. Use Value: Enables full battery capacity utilization (down to 2.3 V) while maintaining <15-mV ripple in PWM mode at 500 mA. |
| Ni-Rich Battery Systems | Si-Anode Portable Devices |
|
Use Scenario: Next-gen smartphone using nickel-rich NMC cathode with flat discharge curve and high energy density. IC Role / Device Role / Timing Role: Voltage translator and current amplifier ensuring constant 3.35-V output despite 3.4–4.35-V battery swing. Use Value: Eliminates need for conservative battery cut-off (e.g., 3.4 V), increasing usable capacity by ~8% over conventional solutions. |
Use Scenario: Ultra-thin wearable with silicon-anode battery exhibiting large voltage hysteresis and low terminal voltage under load. IC Role / Device Role / Timing Role: Adaptive front-end compensating for voltage depression during high-current draw via real-time boost activation. Use Value: Delivers regulated 3.35-V output even when battery sags to 2.65 V under 4-A pulse, extending runtime per charge cycle. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar battery front-end DC/DC converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS61280DYFFR | Same YFF package and pinout; uses 1.8-V I/O logic (VIH = 1.2 V), 3-A valley current limit, and RST/FAULT GPIO default instead of mode-select. | Better suited for legacy 1.8-V host interfaces and systems requiring fault interrupt signaling rather than low-noise mode control. | Select TPS61280DYFFR if I²C host operates at 1.8 V and fault monitoring is prioritized over noise-sensitive PWM forcing. |
| TPS61282DYFFR | Logic-control interface (no I²C); 4-A valley current limit; VSEL thresholds at 3.3 V / 3.5 V; GPIO defaults to RST/FAULT. | Targeted at cost-sensitive designs where firmware-based configuration is unnecessary and simple enable/control suffices. | Choose TPS61282DYFFR when I²C complexity is undesirable and 4-A peak capability with fixed thresholds meets system requirements. |
Compared with TPS61280DYFFR and TPS61282DYFFR, the TPS61280EYFFR uniquely combines 1.2-V I/O compatibility, 5-A current limit, and GPIO-as-mode-select functionality-making it optimal for next-generation mobile SoCs with tight voltage margins and noise-critical subsystems.
Availability
TPS61280EYFFR is available at Aetrix Electronics and suitable for smartphone power management, tablet PC battery interface, and Ni-rich/Si-anode portable devices requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for TPS61280EYFFR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in battery-powered system solutions.
The TPS6128x series was designed specifically for high-efficiency, space-constrained mobile front-end power conversion-addressing the voltage and current challenges of advanced Li-ion chemistries in smartphones and tablets.
FAQ
What is the maximum peak output current supported by the TPS61280EYFFR?
The TPS61280EYFFR supports ≥4-A peak output current at VOUT = 3.35 V with VIN ≥ 2.65 V. Its programmable valley inductor current limit is factory-set to 5 A, providing headroom for transient surges beyond nominal rating. This is confirmed in Section 6 (Device Comparison Table) and Section 8.5 (Electrical Characteristics) of the official datasheet.
Does the TPS61280EYFFR support true pass-through mode during shutdown?
Yes, the TPS61280EYFFR enters true pass-through mode during shutdown with only 3-µA quiescent current. In this state, the internal 35-mΩ FET connects VBAT directly to VOUT while disabling all switching and control circuitry - verified in Section 3 (Description) and Section 8.5 (ISD specification).
How does the TPS61280EYFFR differ from the TPS61280DYFFR in terms of GPIO functionality?
The TPS61280EYFFR configures GPIO (A2) as a mode-selection input by default, enabling PWM-only or PFM/PWM operation. In contrast, the TPS61280DYFFR defaults GPIO to RST/FAULT - an open-drain interrupt output. This distinction is explicitly defined in Table 7-1 (Pin Functions) and Section 6 (Device Comparison Table).
What I²C speeds does the TPS61280EYFFR support, and what are the voltage requirements?
The TPS61280EYFFR supports I²C up to 3.4 Mbps in High-Speed mode and is compatible with 1.2-V I/O logic (VIH = 0.84 V, VIL = 0.36 V). This enables direct interfacing with low-voltage application processors without level-shifting - specified in Section 6 (Device Comparison Table) and Section 8.5 (Input Voltage specs).
Can the TPS61280EYFFR operate with a silicon-anode battery?
Yes, the TPS61280EYFFR is explicitly qualified for silicon-anode batteries, as stated in the title "TPS6128xD/E Low-IQ, Wide-Voltage Battery Front-End DC/DC Converter for Single-Cell Li-Ion, Ni-Rich, Si-Anode Applications" and Section 2 (Applications). Its wide 2.3–4.85-V input range accommodates the low-voltage sag characteristic of Si-anode cells.
TPS61280EYFFR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-UFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Up
- Output Configuration:
- Positive
- Topology:
- Boost
- Output Type:
- Programmable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.3V
- Voltage - Input (Max):
- 4.85V
- Voltage - Output (Min/Fixed):
- 2.85V
- Voltage - Output (Max):
- 4.4V
- Current - Output:
- 4A
- Frequency - Switching:
- 2.3MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-DSBGA (1.67x1.67)
TPS61280EYFFR FAQ
1.How can I place an order for TPS61280EYFFR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS61280EYFFR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS61280EYFFR reliable?
The price and inventory of TPS61280EYFFR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS61280EYFFR is usually 5 days.
3.What payment methods are accepted for TPS61280EYFFR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS61280EYFFR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS61280EYFFR?
TPS61280EYFFR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS61280EYFFR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS61280EYFFR?
For technical support, including TPS61280EYFFR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS61280EYFFR requirements.
6.How does Aetrix verify that TPS61280EYFFR is sourced from the original manufacturer or authorized distributors?
All TPS61280EYFFR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS61280EYFFR meets industry standards.
7.What is the process for return or replacement of TPS61280EYFFR?
All TPS61280EYFFR units undergo pre-shipment inspection (PSI). If there is an issue with TPS61280EYFFR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS61280EYFFR part is unused and in its original packaging.
Return procedure for TPS61280EYFFR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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