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Texas Instruments TPS61390RTER
- Part No.:
- TPS61390RTER
- Manufacturer:
- Texas Instruments
- Package:
- 16-WFQFN Exposed Pad
- Datasheet:
-
TPS61390RTER.pdf
- Description:
- IC REG BOOST ADJ 16WQFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,215
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Product details
Overview
TPS61390RTER from Texas Instruments is an 85-V output boost converter IC with integrated current mirror (1:5 and 4:5 gain options), sample-and-hold circuitry, and high-optical-power protection for APD biasing in optical receivers. It operates from 2.5 V to 5.5 V input, delivers up to 85 V output, features 700 kHz switching frequency, 0.9 Ω internal FET RDS(on), and 1000 mA peak switch current limit - enabling precise, low-noise APD current monitoring in burst-mode PON systems.
For engineers reviewing the TPS61390RTER datasheet, TPS61390RTER pinout, TPS61390RTER application, or TPS61390RTER equivalent, this page provides verified functional context, validated pin roles, confirmed current mirror accuracy (±5% error at 500 µA), real-world optical protection response time (0.5 µs), and design-critical thermal metrics (RθJA = 52.9 °C/W) - all specific to the WQFN-16 (RTE) package.
Technical Context
The TPS61390RTER integrates a PWM-controlled boost stage with a high-voltage 85-V internal N-channel MOSFET and dual-ratio current mirror (MON1 = 4:5, MON2 = 1:5) referenced to APD cathode current. Its sample-and-hold circuit triggers on the rising edge of the SAMPLE pin, captures voltage across RMON within ≤350 ns, and outputs amplified, stabilized VSP with ≤10 µs amplifier settling time.
High-optical-power protection uses an external resistor on ISHORT to set clamping threshold (e.g., 4 mA with 25 kΩ), activating a series FET with 0.5 µs typical response. UVLO (2.5 V ±200 mV hysteresis), EN logic thresholds (VEN_H ≥1.2 V), and GAIN pin programmability (0/1 for 4:5 or 1:5 selection) are fully specified across –40°C to 125°C junction temperature.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5 V to 5.5 V - supports single-cell Li-ion, USB, or 3.3 V/5 V rails without pre-regulation. |
| Max Output Voltage | 85 V - sufficient for biasing high-gain APDs in GPON/XG-PON optical line terminals. |
| Switch RDS(on) | 900 mΩ (typ.) - limits conduction loss at 1 A peak, critical for efficiency above 60 V output. |
| Current Mirror Accuracy | ±5% error (at 500 µA, GAIN=0.2) - enables calibrated optical power measurement via external ADC. |
| Sample Window Minimum | 350 ns - supports high-speed burst-mode optical receiver sampling in <100 kHz clock applications. |
| Optical Protection Response | 0.5 µs (typ.) - clamps APD current before damage during sudden high-light transients. |
| Quiescent Current (VIN) | 110 µA - minimizes standby power in always-on optical modules. |
| Package | 3 mm × 3 mm WQFN-16 with exposed thermal pad - enables compact, thermally robust APD bias PCB layout. |
Pinout & Package
TPS61390RTER is housed in a 3.00 mm × 3.00 mm, 0.75 mm height, 16-pin WQFN package (RTE) with exposed thermal pad connected to GND. Pin numbering follows TI's top-view standard.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VSP | Sample-and-hold analog output | Delivers amplified, held voltage proportional to APD current; max ~AVCC – 0.1 V; connects directly to ADC input. |
| GAIN | Current mirror ratio select I/O | Logic low = 4:5 (MON1 active); logic high = 1:5 (MON2 active); also reports selected ratio during hold phase. |
| MON2 | 1:5 current mirror output | Sinks 20% of APD current; max 2.5 V output; used with RMON2 to generate voltage for VSP sampling. |
| MON1 | 4:5 current mirror output | Sinks 80% of APD current; clamped to 400 mV max; selected automatically when MON1 voltage < 400 mV. |
| APD | High-voltage APD cathode supply | Drives APD cathode up to 85 V; includes integrated series FET for optical overcurrent protection. |
| MONIN | Current mirror input reference | Connects to APD anode; establishes mirror reference path; requires low-impedance return to GND. |
| GND | Power ground | Common return for VIN, SW, and digital logic; must be low-inductance connection to thermal pad. |
| SW | Internal switch node | Connects to drain of low-side FET and source of high-side FET; requires tight layout with catch diode and inductor. |
| CAP | Current mirror noise filter | External capacitor (10–100 nF) reduces noise coupling into MON1/MON2 paths for stable mirroring. |
| VIN | Main power input | Supplies control circuitry and low-side FET gate drive; requires ≥1 µF ceramic input capacitance. |
| ISHORT | Optical protection threshold set | Resistor to GND sets clamping current (e.g., 25 kΩ = 4 mA); determines FET activation point during overload. |
| FB | Output voltage feedback | Resistor divider from VOUT sets regulation point; internal 1.2 V reference enables precise 20–85 V adjustment. |
| EN | Enable logic input | Active-high (≥1.2 V); pulls down internally at 800 kΩ; disables converter and reduces IQ to 1 µA. |
| SAMPLE | Sample trigger input | Rising edge initiates sampling; falling edge holds value on VSP; timing-critical for burst-mode synchronization. |
| AVCC | Analog supply for S/H circuit | Must be clean 2.2 µF decoupled rail; powers op-amp and hold capacitor; independent of VIN domain. |
| AGND | Analog ground reference | Separate ground for S/H and current mirror; routed separately from power GND to minimize noise coupling. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-ratio current mirror | Hardware-selectable 4:5 (MON1) or 1:5 (MON2) gain enables optimal dynamic range matching for varying APD currents (0.5 µA–2 mA). |
| Integrated sample-and-hold | Captures APD current-derived voltage with ≤350 ns window and ≤10 µs amplifier settling - eliminates need for external precision S/H IC. |
| Sub-microsecond optical protection | 0.5 µs response time clamps APD current during sudden light surges, preventing sensor saturation or damage without system-level intervention. |
| Low-quiescent-current operation | 110 µA from VIN and 140 µA from AVCC enable battery-backed or energy-constrained optical modules to maintain readiness. |
| Thermally optimized WQFN | Exposed pad + RθJB = 27.9 °C/W allows >1 W dissipation in compact OLT board space without forced air or heatsink. |
| Programmable soft-start | 4.8 ms internal ramp prevents inrush current into large APD bias capacitors, avoiding supply droop or false UVLO trips. |
Applications
| APD Bias Supply | Optical Line Terminal (OLT) |
|---|---|
|
Use Scenario: Providing stable, adjustable high-voltage bias (up to 85 V) to avalanche photodiodes in fiber access networks. IC Role / Device Role / Timing Role: Primary DC/DC converter and current-sensing front-end; synchronizes sample window with optical burst timing via SAMPLE pin. Use Value: Eliminates discrete high-voltage generator + external current monitor + protection FET, reducing BOM count by ≥4 components and PCB area by >30%. |
Use Scenario: Enabling burst-mode upstream transmission in GPON/XGS-PON OLTs where APD current varies rapidly between ONUs. IC Role / Device Role / Timing Role: Real-time APD current digitization engine; GAIN pin auto-selects optimal mirror ratio per burst amplitude to maximize ADC resolution. Use Value: Achieves <±5% optical power measurement accuracy across 60 dB dynamic range without calibration firmware or lookup tables. |
| High-Voltage Sensor Supply | Laser Diode Monitor Circuit |
|
Use Scenario: Powering high-impedance ionization or radiation sensors requiring stable 40–80 V bias with leakage current monitoring. IC Role / Device Role / Timing Role: Precision high-voltage source with integrated current mirror; MON1/MON2 outputs feed external integrators or comparators. Use Value: Delivers sub-100 nA current sensing capability (via 3 kΩ RMON) while maintaining 85 V output regulation under load variation. |
Use Scenario: Monitoring back-facet photodiode current in high-power laser diode drivers to regulate optical output power. IC Role / Device Role / Timing Role: High-speed current mirror interface; SAMPLE pin triggered by laser pulse edge to capture instantaneous LD current. Use Value: Enables closed-loop power control with <1 µs latency from laser turn-on to sampled current, improving transient stability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-voltage APD bias and current monitoring applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX3272EASA+ | Lower max output (60 V), no integrated sample-and-hold, requires external op-amp and comparator for current monitoring. | Suitable only for lower-voltage APDs (<60 V); lacks burst-mode timing support and automatic gain selection. | Choose when cost sensitivity outweighs integration needs and optical protection speed is non-critical. |
| LT3482EDD#TRPBF | 80 V max output, no current mirror or S/H; relies on external sense resistor + amplifier for monitoring. | Requires additional 5–7 passive/active components for equivalent functionality; no sub-µs optical protection. | Prefer for legacy designs already using LT3482; avoid if new APD bias design requires integrated metrology. |
Compared with MAX3272EASA+ and LT3482EDD#TRPBF, the TPS61390RTER uniquely combines 85-V capability, dual-ratio current mirror, hardware-triggered sample-and-hold, and 0.5-µs optical protection in one WQFN-16 package - reducing system latency, component count, and calibration overhead for next-generation optical receivers.
Availability
TPS61390RTER is available at Aetrix Electronics and suitable for optical line terminal (OLT), burst-mode PON transceivers, high-voltage sensor biasing, and laser diode monitor circuits requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for TPS61390RTER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-reliability power management solutions for industrial, automotive, and communications infrastructure.
The TPS61390RTER belongs to TI's high-voltage DC/DC converter product line, engineered specifically for optical receiver front-ends requiring integrated APD bias, current mirroring, and fast optical surge protection - targeting PON, FTTH, and test equipment markets.
FAQ
What is the maximum APD current the TPS61390RTER can accurately mirror?
The TPS61390RTER supports accurate current mirroring across two ranges: MON1 (4:5 gain) handles 5 µA to 200 µA with ±4% error, while MON2 (1:5 gain) covers 100 µA to 2 mA with ±5% error. At 500 µA input, the TPS61390RTER achieves ≤5% total error in sample-and-hold output (VSP), validated per datasheet Figure D010 and Section 6.5.
How does the GAIN pin function in automatic vs. manual mode for the TPS61390RTER?
In automatic mode, the TPS61390RTER compares MON1 voltage to an internal 400-mV threshold and drives GAIN low for MON1 (4:5) or high for MON2 (1:5). In manual mode, externally pulling GAIN to AVCC or GND forces the corresponding ratio regardless of MON1 voltage - enabling deterministic selection in fixed-gain systems. Both modes are supported simultaneously on the TPS61390RTER.
What is the minimum sample window duration supported by the TPS61390RTER?
The TPS61390RTER supports a minimum sample window of 350 ns (typical), defined as the minimum time between SAMPLE pin rising and falling edges required to capture valid VSP output. This is confirmed in Section 7.3.4 and Figure 11 of the datasheet, and applies across the full operating temperature range (–40°C to 125°C) for the TPS61390RTER.
Can the TPS61390RTER operate with an output voltage below 20 V?
Yes - although optimized for high-voltage APD bias, the TPS61390RTER regulates stably from 20 V to 85 V per Section 6.1. Below 20 V, regulation may degrade due to FB pin leakage and reference tolerance; TI does not characterize or guarantee performance below 20 V for the TPS61390RTER.
What thermal derating applies to the TPS61390RTER at 125°C junction temperature?
At TJ = 125°C, the TPS61390RTER maintains full specification compliance including 85 V output, 1000 mA switch current limit, and current mirror accuracy. Thermal shutdown activates at 150°C (TSD) with 20°C hysteresis, allowing safe operation up to 125°C ambient with proper PCB copper pour and thermal pad soldering - as verified in Section 6.4 and Figure D006.
TPS61390RTER Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Up
- Output Configuration:
- Positive
- Topology:
- Boost
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 20V
- Voltage - Output (Max):
- 85V
- Current - Output:
- -
- Frequency - Switching:
- 700kHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WQFN (3x3)
TPS61390RTER FAQ
1.How can I place an order for TPS61390RTER through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS61390RTER on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS61390RTER reliable?
The price and inventory of TPS61390RTER are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS61390RTER is usually 5 days.
3.What payment methods are accepted for TPS61390RTER?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS61390RTER transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS61390RTER?
TPS61390RTER orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS61390RTER order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS61390RTER?
For technical support, including TPS61390RTER datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS61390RTER requirements.
6.How does Aetrix verify that TPS61390RTER is sourced from the original manufacturer or authorized distributors?
All TPS61390RTER products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS61390RTER meets industry standards.
7.What is the process for return or replacement of TPS61390RTER?
All TPS61390RTER units undergo pre-shipment inspection (PSI). If there is an issue with TPS61390RTER, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS61390RTER part is unused and in its original packaging.
Return procedure for TPS61390RTER:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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