Texas Instruments TPS62005DGS
- Part No.:
- TPS62005DGS
- Manufacturer:
- Texas Instruments
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
TPS62005DGS.pdf
- Description:
- IC REG BUCK 1.8V 600MA 10VSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:315
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS62005DGS from Texas Instruments is a fixed-output 1.9 V synchronous step-down DC-DC converter in a 10-pin VSSOP (DGS) package, delivering up to 600 mA output current with >95% peak efficiency at 3.6 V input/2.5 V output, operating from 2 V to 5.5 V input, and featuring pin-programmable current limit and power-good indication. It serves as the primary voltage regulator for low-power portable systems requiring stable, low-noise 1.9 V rail.
For engineers reviewing the TPS62005DGS datasheet, TPS62005DGS pinout, TPS62005DGS application, or TPS62005DGS equivalent, key selection criteria include its fixed 1.9 V output, 600 mA/1.2 A dual current-limit configuration via ILIM, PFM/PWM mode switching, SYNC-controlled noise-performance trade-off, and 50 µA quiescent current in power-save mode.
Technical Context
The TPS62005DGS implements a current-mode synchronous buck topology with integrated P-channel high-side and N-channel low-side MOSFETs, operating at a nominal 750 kHz switching frequency. Its control loop uses internal compensation and features soft-start (1 ms typical), undervoltage lockout (~1.6 V), and 100% duty-cycle dropout operation.
It supports three functional modes: power-save (PFM/PWM auto-switching) when SYNC = GND, forced PWM (fixed-frequency, low-noise) when SYNC = VIN, and external clock synchronization (500–1000 kHz) when SYNC receives CMOS-level signal. The PG open-drain output asserts high when VOUT exceeds 92% of nominal and remains valid after 100 µs post-enable.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.9 V ±4% over load and line; enables direct replacement of 1.9 V LDOs without feedback divider. |
| Input Voltage Range | 2 V to 5.5 V; supports single-cell Li-ion (2.7–4.2 V), 2–3-cell alkaline/NiMH, and USB-powered systems. |
| Max Output Current | 600 mA (ILIM = GND) or 1.2 A (ILIM = VIN); allows scalable current-limit selection per system fault budget. |
| Quiescent Current | 50 µA typical in PFM mode; extends battery life in standby without sacrificing wake-up response. |
| Switching Frequency | 750 kHz nominal (internal) or 500–1000 kHz (synchronized); enables compact 10 µH inductor and low-profile 10 µF ceramic output cap. |
| Efficiency | 95% peak at 3.6 VIN/2.5 VOUT/200 mA; maintains >85% down to 1 mA load due to PFM mode. |
| Power-Good Threshold | 92% of nominal VOUT (1.748 V); provides reliable system reset signaling with 2.5% hysteresis. |
Pinout & Package
TPS62005DGS is housed in a 10-pin VSSOP (DGS) package, 3.00 mm × 3.00 mm body size, with exposed thermal pad (PGND-connected) for enhanced thermal performance in space-constrained portable PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pin 1) | Primary power input | Accepts 2–5.5 V; requires 10 µF ceramic input capacitor placed near pin for EMI suppression and transient response. |
| FC (Pin 2) | High-frequency bypass | Connects 0.1 µF ceramic capacitor to reduce high-frequency noise on input supply path. |
| GND (Pin 3) | Analog ground reference | Provides reference for error amplifier and internal bias; must be separated from PGND in layout. |
| PG (Pin 4) | Open-drain power-good indicator | Asserts high when VOUT ≥1.748 V; requires external pull-up to VOUT for system monitoring/reset sequencing. |
| FB (Pin 5) | Feedback input | Internally connected to 1.9 V reference divider; unused in fixed-output TPS62005DGS (no external resistor needed). |
| ILIM (Pin 6) | Current-limit select | Ground = 600 mA limit; connect to VIN = 1.2 A limit; sets overcurrent protection threshold before thermal shutdown. |
| SYNC (Pin 7) | Mode control input | GND = PFM/PWM auto-switching; VIN = forced PWM; external clock = synchronized operation (500–1000 kHz). |
| EN (Pin 8) | Enable control | Logic high (>1.3 V) enables regulation; logic low (<0.4 V) disables device, reducing IQ to <1 µA. |
| L (Pin 9) | Switch node | Connects to inductor; carries high di/dt switching current; requires short, wide trace and Kelvin connection to PGND. |
| PGND (Pin 10) | Power ground return | Low-impedance return path for inductor current and internal FETs; must be tied to thermal pad and system power ground plane. |
Key Features
| Feature | Design Value |
|---|---|
| Synchronous rectification | Integrated P- and N-channel MOSFETs eliminate external diode, enabling >95% efficiency and reducing thermal load. |
| Antiringing switch (fixed-output only) | Active during DCM to suppress parasitic LC ringing at switch node, lowering EMI without external snubber. |
| Pin-programmable current limit | Dual thresholds (600 mA / 1.2 A) selected by ILIM connection-enables one BOM for multiple current-class designs. |
| 100% duty-cycle operation | Maintains regulation down to VIN – VDS(on) ≈ 1.9 V, supporting ultra-low dropout in battery-critical applications. |
| Internal soft-start | 1 ms typical ramp prevents output overshoot and inrush current during power-up, eliminating need for external timing components. |
Applications
| Cellular Phones | USB-Based DSL Modems |
|---|---|
Use Scenario: Powering baseband processor core voltage rail in 2G/3G feature phones with Li-ion battery input. IC Role / Device Role / Timing Role: Primary 1.9 V step-down regulator supplying CPU core, dynamically adjusting between PFM (idle) and PWM (active) modes. Use Value: 50 µA quiescent current extends standby time; 600 mA capability supports burst transmit loads; PG signal sequences modem boot sequence. |
Use Scenario: Generating 1.9 V supply for USB interface PHY and packet controller in plug-in DSL adapters. IC Role / Device Role / Timing Role: Fixed-output DC-DC converter regulating from 5 V USB bus, with SYNC pin tied to GND for adaptive efficiency. Use Value: 2–5.5 V input range accepts USB voltage tolerance; 10-pin VSSOP fits tight board area; PG output confirms stable 1.9 V before USB enumeration. |
| Digital Cameras | Handheld PCs / PDAs |
Use Scenario: Supplying image sensor analog front-end requiring low-noise, tightly regulated 1.9 V. IC Role / Device Role / Timing Role: Low-EMI synchronous buck converter; SYNC pin tied to VIN to force PWM mode and minimize switching noise coupling into analog circuits. Use Value: Antiringing switch suppresses high-frequency ringing; 95% efficiency reduces heat near optics; 100% duty cycle sustains output during battery sag. |
Use Scenario: Providing 1.9 V logic rail for ARM-based application processors in legacy handheld PCs. IC Role / Device Role / Timing Role: Main system regulator with enable-controlled power sequencing and PG-monitored voltage validation. Use Value: EN pin enables deep-sleep state control; PG output triggers PMIC reset logic; 600 mA headroom supports peripheral expansion slots. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar step-down DC-DC converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62004DGS | Fixed 1.8 V output; identical pinout, package, and feature set. | Requires system redesign if 1.9 V rail is mandatory (e.g., specific ASIC core voltage). | Select when target SoC specifies 1.8 V nominal with ±3% tolerance and higher margin against under-voltage lockout. |
| TPS62008DGS | Fixed 2.5 V output; same DGS package, 600 mA/1.2 A current limit, and SYNC/EN/PG functionality. | Used where higher logic voltage is required (e.g., older DSPs or interface ICs needing 2.5 V I/O). | Choose for systems migrating from 2.5 V to lower voltages but retaining shared PCB footprint and layout. |
Compared with TPS62005DGS, TPS62004DGS offers tighter 1.8 V regulation for newer low-voltage cores, while TPS62008DGS supports legacy 2.5 V interfaces-both retain identical thermal, layout, and control interface compatibility, enabling drop-in voltage variant selection without redesign.
Availability
TPS62005DGS is available at Aetrix Electronics and suitable for cellular phones, USB-based DSL modems, digital cameras, and handheld PCs requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for TPS62005DGS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-efficiency DC-DC conversion for portable and battery-powered systems.
The TPS6200x product line was designed specifically for ultra-low-power, space-constrained portable electronics-delivering high efficiency across wide load ranges using synchronous buck architecture in micro-VSSOP packaging.
FAQ
What is the output voltage tolerance of the TPS62005DGS over temperature and load?
The TPS62005DGS delivers a fixed 1.9 V output with ±4% tolerance across full operating conditions: –40°C to 85°C ambient, 0–600 mA load, and 2–5.5 V input. This specification is confirmed in the Electrical Characteristics table for TPS62005 under "Fixed output voltage" rows, with worst-case deviation measured at 10 mA < IOUT ≤ 600 mA.
Can the TPS62005DGS operate with an input voltage below 2 V?
No-the TPS62005DGS has a minimum recommended input voltage of 2 V per the Recommended Operating Conditions table. Its undervoltage lockout activates below ~1.6 V (typical), and operation below 2 V risks instability or failure to regulate. For sub-2 V inputs, consider TI's TPS6274x series or alternative ultra-low-VIN buck regulators.
How does the ILIM pin affect current limiting in the TPS62005DGS?
The ILIM pin selects between two factory-trimmed current limits: connecting ILIM to GND sets the switch current limit to 600 mA (typical), while connecting it to VIN raises the limit to 1.2 A (typical). This directly determines overcurrent protection threshold and impacts inductor sizing and thermal design-verified in Section 7.5 Electrical Characteristics under "I(LIM) P-channel current limit".
Is the TPS62005DGS pin-compatible with other devices in the TPS6200x family?
Yes-the entire TPS6200x family, including TPS62005DGS, shares identical 10-pin VSSOP (DGS) packaging, pinout, and function mapping per the Pin Configuration and Functions section. This enables hardware reuse across output voltage variants (0.9 V to 3.3 V) and the adjustable TPS62000DGS, provided FB network and output caps are adjusted accordingly.
Does the TPS62005DGS require an external feedback resistor divider?
No-the TPS62005DGS is a fixed-output variant with internal feedback divider configured for 1.9 V; the FB pin is internally connected and must be left unconnected in circuit. External resistors are only required for the adjustable TPS62000DGS, as stated in Section 8.3.2 and Figure 5 of the datasheet.
TPS62005DGS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.8V
- Voltage - Output (Max):
- -
- Current - Output:
- 600mA
- Frequency - Switching:
- 750kHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSSOP
TPS62005DGS FAQ
1.How can I place an order for TPS62005DGS through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS62005DGS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS62005DGS reliable?
The price and inventory of TPS62005DGS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS62005DGS is usually 5 days.
3.What payment methods are accepted for TPS62005DGS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS62005DGS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS62005DGS?
TPS62005DGS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS62005DGS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS62005DGS?
For technical support, including TPS62005DGS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS62005DGS requirements.
6.How does Aetrix verify that TPS62005DGS is sourced from the original manufacturer or authorized distributors?
All TPS62005DGS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS62005DGS meets industry standards.
7.What is the process for return or replacement of TPS62005DGS?
All TPS62005DGS units undergo pre-shipment inspection (PSI). If there is an issue with TPS62005DGS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS62005DGS part is unused and in its original packaging.
Return procedure for TPS62005DGS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS62005DGS Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
