Texas Instruments TPS62134CRGTT

Overview

TPS62134CRGTT from Texas Instruments is a synchronous step-down DC-DC converter optimized for Intel Skylake platform VCC(IO) rail applications, featuring DCS-Control™ architecture, 0.95 V fixed output voltage at up to 3 A, 3–17 V input range, and 20 µA quiescent current in power-save mode.

For engineers reviewing the TPS62134CRGTT datasheet, TPS62134CRGTT pinout, TPS62134CRGTT application, or TPS62134CRGTT equivalent, key selection criteria include LPM-enabled dynamic voltage scaling, VIDx-programmable output (0.85–0.975 V), single-ended remote sense (FBS), power-good timing (140 µs rise delay), and thermal shutdown at 160 °C.

Technical Context

The TPS62134CRGTT implements DCS-Control™ topology-combining hysteretic, voltage-mode, and current-mode regulation with an AC loop directly tied to output voltage-to deliver fast transient response (<30 ns load-step recovery) and ±1% DC output accuracy in PWM mode. It supports seamless transition between 1 MHz PWM operation and variable-frequency power-save mode (PSM) down to 20 µA IQ.

Its functional modes are controlled via dedicated pins: LPM enables low-power voltage reduction (0 V output), VID0/VID1 select one of five output voltages (0.85–0.975 V), EN provides sequencing control with 400 kΩ internal pulldown, and FBS enables single-ended remote sensing at the load to compensate for PCB trace resistance.

Key Specifications

Pinout & Package

TPS62134CRGTT is housed in a thermally enhanced 3-mm × 3-mm VQFN-16 package with exposed thermal pad (RGT suffix), requiring soldering to AGND/PGND planes for thermal management and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar step-down converter applications.

Compared with TPS62134CRGTT, TPS62134BRGTT delivers lower nominal output (0.90 V) for core rails, while TPS62134DRGTT retains 0.95 V but enables 0.7 V LPM-both require no PCB changes but demand verification of VID mapping and LPM behavior in system firmware.

Availability

TPS62134CRGTT is available at Aetrix Electronics and suitable for Intel Skylake platform designs, solid-state disk drive power supplies, and 12-V intermediate rail point-of-load applications requiring stable component supply across production lifecycles.

Supply support for TPS62134CRGTT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with over 50 years of innovation in high-reliability power conversion solutions.

The TPS62134x product line was designed specifically for Intel Skylake platform voltage regulation requirements-including VCC(IO), VCC(PRIM_CORE), and VCC(EDRAM) rails-with emphasis on fast transient response, low IQ, and seamless PSM/PWM mode transitions.

FAQ

What is the nominal output voltage of the TPS62134CRGTT and how is it configured?

The TPS62134CRGTT is factory-configured for a nominal 0.95 V output, achieved when VID0 and VID1 are both driven high (per Table 1 in the datasheet). This setting is fixed for the 'C' variant and does not require external resistors. The TPS62134CRGTT maintains ±1% DC accuracy in PWM mode and supports dynamic voltage scaling via the LPM pin, which pulls output to 0 V when asserted.

Does the TPS62134CRGTT support remote sensing, and how is it implemented?

Yes, the TPS62134CRGTT supports single-ended remote sensing via the FBS pin. To implement it, connect the FBS trace directly to the load's power input node-separate from the main output capacitor-and route it over a solid ground plane. This compensates for voltage drop across PCB traces, improving load regulation to ±0.01%/A. Noise on the FBS trace must be minimized; avoid routing near switching nodes like SW or PGND.

What is the purpose of the LPM pin on the TPS62134CRGTT, and what happens to PG during LPM assertion?

The LPM (Low-Power Mode) pin on the TPS62134CRGTT enables system-level power state coordination: when pulled low, it forces the output voltage to 0 V and places the PG pin in high-impedance state. Upon exiting LPM, PG remains blanked for 500 µs to allow output stabilization before signaling validity. For TPS62134CRGTT, this behavior is documented for LPM transitions where VO exits the 0.5–0.75 V range, requiring careful firmware timing.

How does the TPS62134CRGTT manage efficiency across load conditions?

The TPS62134CRGTT uses DCS-Control™ to operate in 1 MHz PWM mode under medium/heavy loads and automatically transitions to power-save mode (PSM) at light loads. In PSM, switching frequency scales linearly with load current, sustaining >85% efficiency down to 1 mA. Its 20 µA quiescent current and optimized MOSFET rDS(on) (90 mΩ high-side, 40 mΩ low-side) ensure minimal no-load loss and high light-load performance without external bias circuits.

What thermal management considerations apply to the TPS62134CRGTT in a 3 mm × 3 mm VQFN package?

The TPS62134CRGTT's RGT package features an exposed thermal pad that must be soldered to a minimum 100 mm² copper area connected to AGND and PGND planes. With θJA = 44.2 °C/W, full 3.2 A operation requires ≤40 °C ambient or supplemental airflow. Thermal shutdown activates at 160 °C (140 °C hysteresis), and layout must minimize thermal resistance between the pad and PCB copper-avoid thermal relief spokes and use ≥6 vias (0.3 mm diameter) to inner ground layers.