Texas Instruments TPS62313YZDR
- Part No.:
- TPS62313YZDR
- Manufacturer:
- Texas Instruments
- Package:
- 8-UFBGA, DSBGA
- Datasheet:
-
TPS62313YZDR.pdf
- Description:
- IC REG BUCK 1.8V 500MA 8DSBGA
- Quantity:
- Payment:

- Shipping:

Inventory:3,816
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS62313YZDR from Texas Instruments is a 500-mA, 3-MHz synchronous step-down DC-DC converter in an 8-pin NanoFree™ CSP package, delivering fixed 1.8 V output from 2.7–6 V input. It features 93% peak efficiency, 86-µA quiescent current in power-save mode, and supports on-the-fly synchronization to external clocks. It serves as the core power supply for low-voltage DSPs and application processors in space-constrained portable electronics.
For engineers reviewing the TPS62313YZDR datasheet, TPS62313YZDR pinout, TPS62313YZDR application, or TPS62313YZDR equivalent, key selection criteria include its 1.8 V fixed output, 3-MHz switching frequency with PFM/PWM auto-transition, ultra-low profile CSP-8 packaging, and integrated active power-down sequencing capability.
Technical Context
The TPS62313YZDR employs voltage-mode control with input voltage feed-forward to achieve best-in-class load and line transient response. Its dual MOSFET current limiting (P-MOS at 670–890 mA, N-MOS sourcing at 550–890 mA) enables stable operation across wide duty cycles, including low-VOUT/high-VIN conditions.
It operates in fixed-frequency 3-MHz PWM mode under medium-to-heavy loads and automatically transitions to pulse-frequency modulation (PFM) at light loads-reducing quiescent current to 86 µA while maintaining regulation via ±1.5% output ripple threshold detection. The MODE/SYNC pin enables forced PWM, external synchronization, or automatic PFM/PWM selection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.8 V ±0.5% over –40°C to +85°C - ensures stable core voltage for ARM Cortex-A/M cores and TI TMS320 DSPs. |
| Switching Frequency | 3 MHz (2.65–3.35 MHz range) - enables use of sub-1-µH inductors and <10-µF ceramic output capacitors for minimal PCB footprint. |
| Max Output Current | 500 mA continuous - sufficient for single-core application processors and baseband ICs in smartphones and PDAs. |
| Quiescent Current | 86 µA in PFM mode - extends battery life in standby/sleep states without compromising wake-up response. |
| Input Voltage Range | 2.7 V to 6 V - compatible with single-cell Li-ion (2.7–4.2 V), 3-cell NiMH/NiCd (3.6–4.5 V), and USB-powered systems. |
| Undervoltage Lockout | 2.0 V threshold - prevents erratic operation during brownout and ensures clean startup after battery recovery. |
| Thermal Shutdown | 150°C with 20°C hysteresis - protects device during sustained overload or poor thermal layout without latch-up. |
Pinout & Package
TPS62313YZDR uses an 8-pin NanoFree™ Chip Scale Package (CSP-8), measuring 1.5 mm × 1.5 mm × 0.55 mm - optimized for ultra-thin mobile devices requiring minimal board area and height. The package features bottom-side solder bumps aligned to JEDEC MO-220 standards.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN | Power input | Connects directly to input bypass capacitor; supplies power stage; rated for 2.7–6 V with 7-V absolute max. |
| EN | Enable control | Active-high logic input; must be terminated (not floating); pulls device into <1-µA shutdown when grounded. |
| ADJ | Adjust reference input | Not connected on fixed-output TPS62313YZDR; internal feedback divider is enabled; pin left unconnected per datasheet. |
| FB | Feedback sense | Internally tied to regulated 0.4-V reference; not accessible on fixed-output version; pin left unconnected. |
| VOUT | Output sense | Direct connection to output rail; used for remote sensing in high-accuracy applications; requires low-impedance path. |
| MODE/SYNC | Mode control & sync input | Configures PFM/PWM auto-switching (GND), forced PWM (VIN), or external clock sync (3-MHz square wave). |
| PGND | Power ground | Primary return path for high-current switch node; must be routed with low-inductance copper to minimize noise. |
| SW | Switch node | Drain connection of internal P/N-MOSFET pair; connects to external inductor; requires tight layout to reduce EMI. |
Key Features
| Feature | Design Value |
|---|---|
| 3-MHz fixed-frequency operation | Enables use of 0.9–2.2 µH chip inductors and 4.7–10 µF X5R/X7R ceramics - reduces solution size by >40% vs. 1-MHz converters. |
| Power-save mode with 86-µA IQ | Maintains >85% efficiency down to 1 mA load - critical for always-on subsystems like RTC, sensors, and Bluetooth radios. |
| On-the-fly MODE/SYNC control | Allows dynamic switching between low-noise PWM and high-efficiency PFM during runtime - supports adaptive power management. |
| 100% duty cycle capability | Supports dropout as low as VOUT + 0.5 V (min 2.7 V input) - extends usable battery range in Li-ion discharge curve. |
| Integrated soft-start | Controls inrush current during startup - eliminates need for external RC timing network and prevents input rail sag. |
| NanoFree™ CSP-8 packaging | 1.5 × 1.5 × 0.55 mm footprint with 0.5-mm pitch - enables placement under narrow-pitch BGA processors or in camera module modules. |
Applications
| Smartphone Application Processor Core Rail | Bluetooth/WLAN Baseband Power |
|---|---|
Use Scenario: Powers ARM Cortex-A8/A9 core logic in smartphone SoCs requiring tightly regulated 1.8 V at up to 500 mA. IC Role / Device Role / Timing Role: Primary buck regulator supplying CPU core voltage; operates in PFM during idle, PWM during burst compute. Use Value: Delivers 93% efficiency at 300 mA and maintains <25-mV P-P ripple - ensuring stable clock domain operation and low thermal dissipation. |
Use Scenario: Supplies 1.8 V to Bluetooth 4.0 and 802.11n baseband ICs in handheld and wearable devices. IC Role / Device Role / Timing Role: Dedicated point-of-load regulator with fast load transient response (<2 µs settling) for RF packet bursts. Use Value: Achieves <50-mV undershoot/overshoot during 10–100 mA load steps - preventing RF desense and link dropouts. |
| Digital Camera Image Sensor Bias | USB DSL Modem PHY Interface |
Use Scenario: Provides clean 1.8 V bias to CMOS image sensor analog front-end and column ADC drivers. IC Role / Device Role / Timing Role: Low-noise power source with forced PWM mode (MODE/SYNC = VIN) to suppress switching frequency interference. Use Value: Enables <–65 dBc PSRR at 3 MHz - reducing switching artifacts in image data and improving SNR by ≥3 dB. |
Use Scenario: Powers USB 2.0 transceiver and DSL line driver interface circuitry in compact broadband modems. IC Role / Device Role / Timing Role: Input-supply-synchronized buck converter supporting 3-MHz clock alignment with USB SOF timing. Use Value: Allows deterministic EMI filtering via fixed 3-MHz fundamental - simplifying FCC Class B compliance without spread-spectrum. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62303YZD | Same CSP-8 package and 1.8 V fixed output, but UVLO threshold is 2.4 V (vs. 2.0 V for TPS62313YZDR) and lacks active power-down sequencing. | Less suitable for deep-discharge Li-ion systems below 2.4 V; no integrated discharge path for controlled VOUT ramp-down. | Select TPS62303YZD only if UVLO margin above 2.4 V is guaranteed and power-down sequencing is handled externally. |
| TPS62315YZ | Identical CSP-8 package and 3-MHz architecture, but delivers 1.875 V output with ±0.5% accuracy and same 2.0-V UVLO. | Designed for TI OMAP-L1x and C674x DSP core rails requiring 1.875 V; incompatible where strict 1.8 V tolerance is mandated. | Choose TPS62315YZ only when system-level voltage margin allows +42 mV offset and 1.875 V is specified in processor datasheet. |
Compared with TPS62303YZD and TPS62315YZ, the TPS62313YZDR offers the lowest UVLO (2.0 V) among 1.8 V variants and includes active power-down sequencing - making it optimal for battery-powered systems requiring extended runtime and controlled shutdown behavior.
Availability
TPS62313YZDR is available at Aetrix Electronics and suitable for smartphone power management, Bluetooth/WLAN baseband supplies, digital camera sensor biasing, and USB DSL modem PHY interfaces requiring stable component supply and long-term lifecycle support.
Supply support for TPS62313YZDR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC-DC conversion for portable electronics.
The TPS623xx family was designed specifically for space-constrained, battery-powered applications demanding high-frequency operation, ultra-low quiescent current, and minimal solution footprint - targeting smartphones, PDAs, and wireless modules.
FAQ
What is the recommended inductor value for TPS62313YZDR in a typical 1.8 V/500 mA application?
The TPS62313YZDR is optimized for 0.9 µH to 2.2 µH chip inductors. For best efficiency and transient response at 500 mA, TI recommends the FDK MIPW3226 series 1.0 µH inductor with 0.045 Ω DCR. Using 1.0 µH achieves 93% peak efficiency at 300 mA with 4.7 µF X5R output capacitance and meets all load transient specifications per Figure 9–12 in the SLVS528E datasheet.
Does TPS62313YZDR support external synchronization, and what are the signal requirements?
Yes, TPS62313YZDR supports external synchronization via the MODE/SYNC pin. It accepts a 3-MHz (±0.35 MHz) square wave with 20%–80% duty cycle and TTL-compatible logic levels (VIL ≤ 0.4 V, VIH ≥ 1.3 V). Synchronization aligns the P-channel MOSFET turn-on edge to the falling edge of the external clock, enabling deterministic multi-rail phase alignment in complex PMIC designs.
Can TPS62313YZDR operate with input voltage below 2.7 V, and what happens near UVLO?
TPS62313YZDR has a 2.0 V undervoltage lockout (UVLO) threshold with hysteresis. It remains operational down to ~2.0 V input, but output regulation degrades below 2.7 V due to reduced headroom. Below 2.0 V, the device shuts down completely, drawing <1 µA. Recovery occurs only after VIN rises above 2.2 V (2.0 V + 0.2 V hysteresis), ensuring clean restart without oscillation.
How does the power-save mode of TPS62313YZDR affect output voltage accuracy and ripple?
In power-save (PFM) mode, TPS62313YZDR regulates output voltage by allowing VOUT to dip to –1.5% of nominal before initiating a burst of switching cycles. This results in typical 25-mVP-P ripple at light loads (1–10 mA), with average VOUT remaining within ±0.5% of 1.8 V. The trade-off is higher low-frequency ripple versus 86-µA quiescent current - ideal for battery-sensitive always-on functions.
Is TPS62313YZDR pin-compatible with other members of the TPS623xx family in CSP-8 packaging?
Yes, all TPS623xx devices in the CSP-8 package (including TPS62303YZD, TPS62311YZD, TPS62313YZDR, TPS62315YZ, and TPS62321YZD) share identical pinout, footprint, and solder bump layout per the "CSP-8 (TOP VIEW)" diagram in SLVS528E. This enables direct substitution for different output voltages without PCB redesign - provided UVLO, accuracy, and sequencing requirements are verified.
TPS62313YZDR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-UFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.7V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 1.8V
- Voltage - Output (Max):
- -
- Current - Output:
- 500mA
- Frequency - Switching:
- 3MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-DSBGA
TPS62313YZDR FAQ
1.How can I place an order for TPS62313YZDR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS62313YZDR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS62313YZDR reliable?
The price and inventory of TPS62313YZDR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS62313YZDR is usually 5 days.
3.What payment methods are accepted for TPS62313YZDR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS62313YZDR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS62313YZDR?
TPS62313YZDR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS62313YZDR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS62313YZDR?
For technical support, including TPS62313YZDR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS62313YZDR requirements.
6.How does Aetrix verify that TPS62313YZDR is sourced from the original manufacturer or authorized distributors?
All TPS62313YZDR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS62313YZDR meets industry standards.
7.What is the process for return or replacement of TPS62313YZDR?
All TPS62313YZDR units undergo pre-shipment inspection (PSI). If there is an issue with TPS62313YZDR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS62313YZDR part is unused and in its original packaging.
Return procedure for TPS62313YZDR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS62313YZDR Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

