Texas Instruments TPS62402DRCR
- Part No.:
- TPS62402DRCR
- Manufacturer:
- Texas Instruments
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TPS62402DRCR.pdf
- Description:
- IC REG BUCK PROG/3.3V DL 10VSON
- Quantity:
- Payment:

- Shipping:

Inventory:8,370
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Product details
Overview
TPS62402DRCR from Texas Instruments is a dual synchronous step-down DC-DC converter IC optimized for portable battery-powered systems, delivering 400 mA on Channel 1 (default 1.2 V) and 600 mA on Channel 2 (default 3.3 V) across 2.5–6 V input, operating at 2.25 MHz fixed frequency with ±1% output voltage accuracy in PWM mode.
For engineers reviewing the TPS62402DRCR datasheet, TPS62402DRCR pinout, TPS62402DRCR application, or TPS62402DRCR equivalent, key selection criteria include dual-rail dynamic voltage scaling support via DEF_1 pin, EasyScale™ one-wire interface capability, 180° out-of-phase operation to reduce input ripple, and VSON-10 (3 mm × 3 mm) package suitability for space-constrained mobile power designs.
Technical Context
The TPS62402DRCR integrates two independent current-mode synchronous buck regulators sharing a single 2.25-MHz oscillator with 180° phase shift-reducing input RMS current and enabling smaller input capacitors. Each channel features internal PMOS/NMOS power switches with typical RDS(ON) of 280 mΩ / 200 mΩ and integrated short-circuit protection via dual current limits.
Operation supports three functional modes: automatic PFM/PWM transition (MODE/DATA = GND), forced-PWM (MODE/DATA = high), and shutdown (EN1/EN2 = low). Output voltage selection for Channel 1 is digital via DEF_1 pin (1.2 V low, 1.1 V high); Channel 2 is fixed at 3.3 V, requiring ADJ2 tied directly to VOUT2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 2.5 V to 6 V - supports single-cell Li-ion (3.0–4.2 V) and regulated 3.3 V/5 V rails without external LDO pre-regulation. |
| Output 1 (VOUT1) | Fixed 1.2 V @ 400 mA - default set by DEF_1 = low; enables core voltage supply for low-power DSPs or ARM Cortex-M processors. |
| Output 2 (VOUT2) | Fixed 3.3 V @ 600 mA - requires ADJ2 connected directly to VOUT2; suitable for I/O, memory, or peripheral rail in portable systems. |
| Switching Frequency | 2.25 MHz (±12.5%) - enables use of compact 2.2 μH inductors and ceramic capacitors; reduces solution footprint vs. lower-frequency converters. |
| Quiescent Current | 32 μA (both channels active, PFM mode) - extends battery life in standby/sleep states of handheld devices. |
| Output Accuracy | ±1% in PWM mode - ensures stable logic-level compliance for sensitive digital loads without external trimming. |
| Shutdown Current | 1.2 μA - minimizes battery drain during full system off-state; critical for always-on sensor nodes or backup power paths. |
Pinout & Package
VSON-10 (3 mm × 3 mm) package with exposed PowerPAD™ thermal pad for enhanced heat dissipation in high-density PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ADJ2 | Converter 2 feedback reference | Must be shorted to VOUT2 for fixed 3.3 V operation; not used for resistor programming in TPS62402DRCR. |
| DEF_1 | Digital select for VOUT1 | Low = 1.2 V, High = 1.1 V; enables dual-voltage core scaling without external resistors or firmware changes. |
| EN1, EN2 | Independent enable inputs | Active-high control per channel; allows staggered startup, power sequencing, or selective rail disable for system-level power management. |
| FB1 | Converter 1 feedback sense | Internally connected to fixed-resistor divider; no external components required for 1.2 V/1.1 V outputs. |
| MODE/DATA | Mode control & serial interface | GND = auto PFM/PWM; VIN = forced PWM; also serves as bidirectional EasyScale™ data line for runtime voltage updates. |
| SW1, SW2 | Power switch nodes | Connect to 2.2 μH inductors; require low-ESR ceramic output caps (e.g., 10–22 μF) placed close to pins for stability. |
| VIN | Main power input | Supplies both converters; requires local 10 μF ceramic bypass cap near pin to suppress high-frequency switching noise. |
| GND | Signal & power ground | Shared ground for both converters; must be tied to PowerPAD™ for thermal and EMI performance. |
| PowerPAD™ | Thermal & electrical ground | Exposed copper pad under package; soldered to large PCB ground plane for <20.4°C/W junction-to-board thermal resistance. |
Key Features
| Feature | Design Value |
|---|---|
| 180° out-of-phase operation | Reduces input capacitor RMS current by ~30%, allowing smaller 10 μF input caps instead of 22 μF for same ripple. |
| EasyScale™ one-pin interface | Enables real-time VOUT1/VOUT2 adjustment via MODE/DATA pin without dedicated I²C/SPI lines or additional GPIOs. |
| 100% duty cycle capability | Maintains regulation down to VOUT = VIN − 0.5 V (e.g., 3.3 V out at 3.8 V in), minimizing dropout loss in battery discharge tail-end. |
| Integrated soft-start | Controls VOUT ramp-up time to 750 μs (5–95%), preventing inrush current damage to input caps or upstream power sources. |
| Thermal shutdown with hysteresis | Shuts down at 150°C junction temperature and re-enables at 130°C, protecting against sustained overload in sealed enclosures. |
Applications
| Smartphone Application Processor Core Supply | Portable Medical Sensor Hub |
|---|---|
Use Scenario: Powers ARM-based application processor (e.g., OMAP-L138) requiring dynamically scaled core voltage (1.1–1.2 V) and fixed I/O rail (3.3 V). IC Role / Device Role / Timing Role: Dual-channel buck regulator providing independent, sequenced, and voltage-scalable power domains with sub-μs response to load transients. Use Value: Enables DVFS-driven battery savings via DEF_1 pin toggling and eliminates need for discrete LDOs or external DACs for core voltage control. | Use Scenario: Supplies ultra-low-power MCU (e.g., MSP430FR5994), analog front-end (AFE), and BLE radio in wearable health monitor. IC Role / Device Role / Timing Role: Single-chip dual-rail source replacing two discrete converters; 180° phase shift minimizes conducted EMI into sensitive analog signal paths. Use Value: Achieves >92% efficiency at 10 mA load (PFM mode), extending coin-cell battery life beyond 12 months in continuous-sensing mode. |
| Industrial Handheld Terminal | Automotive Infotainment Display Backlight Driver |
Use Scenario: Powers FPGA fabric (1.2 V), DDR2 memory interface (3.3 V), and touch controller in ruggedized logistics scanner. IC Role / Device Role / Timing Role: Dual-output DC-DC with independent EN1/EN2 enables precise power sequencing during cold boot and graceful shutdown. Use Value: Eliminates external sequencing ICs; 32-μA quiescent current meets EN55022 Class B standby requirements for industrial equipment. | Use Scenario: Generates 3.3 V bias for display timing controller and 1.2 V logic for video decoder ASIC in automotive-grade head unit. IC Role / Device Role / Timing Role: Automotive-qualified dual buck (AEC-Q100 Grade 3) delivering stable rails across -40°C to +85°C ambient with 1.2 V/3.3 V accuracy maintained. Use Value: Replaces discrete solutions with 40% smaller footprint; 2.25-MHz operation avoids AM radio band interference (0.53–1.71 MHz). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-step-down converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62401DRCR | Default outputs: 1.575 V / 1.8 V; DEF_1 selects 1.575 V (low) or 1.1 V (high); ADJ2 tied to VOUT2. | Suitable for OMAP3/DM365-based systems needing 1.575 V core + 1.8 V I/O; not drop-in for 1.2 V/3.3 V requirement. | Select when existing design uses 1.575 V core rail and requires identical pinout/package but different voltage defaults. |
| TPS62403DRCR | Default outputs: 1.575 V / 2.8 V; DEF_1 selects 1.575 V (low) or 1.9 V (high); ADJ2 tied to VOUT2. | Targets applications needing 2.8 V for SDIO or USB PHY; lacks 3.3 V compatibility without external post-regulation. | Choose for systems requiring 2.8 V I/O rail with same footprint; verify 2.8 V sufficiency for all peripherals before substitution. |
Compared with TPS62401DRCR and TPS62403DRCR, the TPS62402DRCR uniquely provides the 1.2 V / 3.3 V combination required for modern low-voltage microcontrollers paired with legacy 3.3 V peripherals, eliminating level-shifting overhead and reducing BOM count.
Availability
TPS62402DRCR is available at Aetrix Electronics and suitable for smartphone power management, portable medical sensors, industrial handheld terminals, and automotive infotainment displays requiring stable component supply with guaranteed long-term sourcing.
Supply support for TPS62402DRCR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with over 50 years of innovation in power management ICs.
The TPS6240x product line was designed specifically for high-efficiency, small-footprint dual-rail power conversion in battery-operated portable electronics, emphasizing dynamic voltage scaling, low quiescent current, and integrated thermal protection.
FAQ
What are the default output voltages configured for TPS62402DRCR?
The TPS62402DRCR is factory-configured with Channel 1 (VOUT1) at 1.2 V (DEF_1 = low) and Channel 2 (VOUT2) at 3.3 V. These are fixed outputs-no external resistors are needed. The ADJ2 pin must be directly connected to VOUT2, and FB1 is internally terminated to maintain regulation accuracy without external components.
Can TPS62402DRCR operate with only one channel enabled?
Yes, TPS62402DRCR supports independent channel control: EN1 enables only Channel 1 (1.2 V), EN2 enables only Channel 2 (3.3 V), and both can be active simultaneously. When one channel is disabled, its quiescent current drops to ≤1.2 μA, while the active channel maintains full regulation and efficiency-ideal for partial-system wake-up scenarios.
Does TPS62402DRCR support dynamic voltage scaling (DVS) during operation?
Yes, TPS62402DRCR supports real-time DVS via its EasyScale™ one-pin serial interface using the MODE/DATA pin. By sending command sequences, the host processor can adjust VOUT1 between 1.1 V and 1.2 V (and VOUT2 if modified from default), enabling adaptive power management without hardware changes or additional communication lines.
What is the recommended inductor value for TPS62402DRCR in standard operation?
The recommended inductor for TPS62402DRCR is 2.2 μH with ≥1.5 A saturation current rating. TI's reference design uses shielded power inductors (e.g., Coilcraft XAL5030-222MEB) to minimize EMI and ensure stable operation at 2.25 MHz. Inductor DCR should be ≤120 mΩ to maintain efficiency above 90% at full load.
How does the 180° phase shift between channels benefit system design?
The 180° phase shift between TPS62402DRCR's two channels reduces input capacitor RMS current by approximately 30%, allowing use of smaller 10 μF ceramic input capacitors instead of larger 22 μF units. This lowers total solution size, cost, and high-frequency noise coupling into sensitive analog sections of the PCB.
TPS62402DRCR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Programmable (Fixed)
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 1.2V, 1.8V (3.3V)
- Voltage - Output (Max):
- -
- Current - Output:
- 400mA, 600mA
- Frequency - Switching:
- 2.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSON (3x3)
TPS62402DRCR FAQ
1.How can I place an order for TPS62402DRCR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS62402DRCR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS62402DRCR reliable?
The price and inventory of TPS62402DRCR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS62402DRCR is usually 5 days.
3.What payment methods are accepted for TPS62402DRCR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS62402DRCR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS62402DRCR?
TPS62402DRCR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS62402DRCR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS62402DRCR?
For technical support, including TPS62402DRCR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS62402DRCR requirements.
6.How does Aetrix verify that TPS62402DRCR is sourced from the original manufacturer or authorized distributors?
All TPS62402DRCR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS62402DRCR meets industry standards.
7.What is the process for return or replacement of TPS62402DRCR?
All TPS62402DRCR units undergo pre-shipment inspection (PSI). If there is an issue with TPS62402DRCR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS62402DRCR part is unused and in its original packaging.
Return procedure for TPS62402DRCR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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