Texas Instruments TPS62402DRCTG4
- Part No.:
- TPS62402DRCTG4
- Manufacturer:
- Texas Instruments
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TPS62402DRCTG4.pdf
- Description:
- IC REG BUCK PROG/3.3V DL 10VSON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
TPS62402DRCTG4 from Texas Instruments is a dual synchronous step-down DC-DC converter IC delivering 400 mA on Channel 1 (VOUT1 = 1.2 V default) and 600 mA on Channel 2 (VOUT2 = 3.3 V default), operating from 2.5 V to 6 V input, with 2.25-MHz fixed-frequency PWM and power-save mode for portable battery-powered systems.
For engineers reviewing the TPS62402DRCTG4 datasheet, TPS62402DRCTG4 pinout, TPS62402DRCTG4 application, or TPS62402DRCTG4 equivalent, key selection considerations include dual-rail voltage flexibility via DEF_1 pin selection, 180° out-of-phase operation to reduce input ripple, ±1% output accuracy in PWM mode, 32-μA typical quiescent current for both converters, and VSON-10 (3 mm × 3 mm) package suitability for space-constrained mobile designs.
Technical Context
The TPS62402DRCTG4 integrates two independent synchronous buck regulators sharing a single 2.25-MHz oscillator with 180° phase shift between SW1 and SW2 to minimize input capacitor RMS current. Each channel uses voltage-mode control with input-voltage feed-forward and internal compensation.
Channel 1 supports pin-selectable fixed outputs (1.2 V / 1.1 V) via DEF_1; Channel 2 is fixed at 3.3 V with ADJ2 tied directly to VOUT2. MODE/DATA enables either automatic PFM/PWM transition or forced-PWM operation, while EN1/EN2 provide independent enable control per channel.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 2.5 V to 6 V - supports single-cell Li-ion (2.7–4.2 V) and standard 3.3-V/5-V rails without external regulation |
| VOUT1 Default | 1.2 V (DEF_1 = Low) - matches core voltage requirements of OMAP™ and low-power DSPs |
| VOUT2 Default | 3.3 V - powers I/O, memory, or peripheral interfaces requiring higher rail stability |
| Output Current | 400 mA (CH1), 600 mA (CH2) - sufficient for dual-rail SoC subsystems with independent load profiles |
| Switching Frequency | 2.25 MHz (±12.5%) - enables use of compact 2.2-μH inductors and ceramic capacitors for minimal PCB footprint |
| Quiescent Current | 32 μA (both channels active, PFM mode) - extends battery life in standby and light-load states |
| Accuracy (PWM) | ±1% over line/load/temp - ensures stable core voltage under dynamic processor load transitions |
Pinout & Package
TPS62402DRCTG4 is housed in a thermally enhanced 10-pin VSON package (3.00 mm × 3.00 mm, 0.5-mm pitch) with exposed PowerPAD™ for improved thermal dissipation (RθJA = 45.9°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DEF_1 (Pin 5) | Digital select input for VOUT1 | Low = 1.2 V, High = 1.1 V - enables dynamic voltage scaling without external resistors |
| EN1 (Pin 7) | Enable for Channel 1 | Active-high control allows independent startup sequencing of core and I/O rails |
| EN2 (Pin 9) | Enable for Channel 2 | Independent enable permits power gating of peripherals during sleep modes |
| MODE/DATA (Pin 2) | Mode control & serial interface | GND = auto PFM/PWM; VIN = forced PWM; also serves as EasyScale™ one-wire bus for runtime VOUT adjustment |
| FB1 (Pin 4) | Feedback for Channel 1 | Internally connected to fixed resistor divider - no external components required for default outputs |
| ADJ2 (Pin 1) | Adjust input for Channel 2 | Must be shorted to VOUT2 - disables external programming and enables fixed 3.3-V operation |
| SW1 (Pin 6), SW2 (Pin 10) | Power switch nodes | Drive external 2.2-μH inductors; 180° phase relationship reduces input capacitor stress |
| VIN (Pin 3), GND (Pin 8), PowerPAD™ | Supply input, ground, thermal pad | PowerPAD™ must be soldered to PCB ground plane for thermal and electrical integrity |
Key Features
| Feature | Design Value |
|---|---|
| 180° out-of-phase switching | Reduces input RMS current by ~30%, allowing smaller input capacitors and lower EMI filtering cost |
| Pin-selectable VOUT1 | Two factory-programmed voltages (1.2 V / 1.1 V) selected via single DEF_1 logic level - eliminates BOM overhead vs adjustable versions |
| Fixed 3.3-V VOUT2 | No external feedback components needed - simplifies layout and improves reliability for I/O rail generation |
| EasyScale™ interface | Runtime reconfiguration of both outputs using only MODE/DATA pin - supports adaptive power management in DSP/processor systems |
| 100% duty cycle capability | Enables ultra-low dropout operation near VIN - critical for maintaining regulation as battery discharges below 3.3 V |
Applications
| Smartphone Application Processor Core Supply | Portable Media Player I/O & Memory Rail |
|---|---|
Use Scenario: Powers ARM-based application processors (e.g., OMAP™) requiring dynamically scalable core voltage between 1.1 V and 1.2 V under varying compute loads. IC Role / Device Role / Timing Role: Dual-channel buck regulator providing independent, sequenced, and voltage-scalable power rails with soft-start and short-circuit protection. Use Value: DEF_1 pin enables hardware-selectable core voltage; 2.25-MHz switching allows <1-mm² inductor footprint; 32-μA quiescent current extends standby time. |
Use Scenario: Supplies 3.3-V I/O and NAND flash memory in handheld media players where stable rail tolerance and low noise are essential for data integrity. IC Role / Device Role / Timing Role: Fixed-output Channel 2 delivers regulated 3.3 V with ±1% accuracy and 100% duty-cycle support for brownout resilience. Use Value: ADJ2 tied to VOUT2 eliminates external resistors; 180° phase shift minimizes input ripple on shared battery source; thermal pad ensures reliable operation at 600-mA load. |
| Digital Camera Image Signal Processor (ISP) Core | Low-Power DSP Subsystem Supply |
Use Scenario: Provides clean, low-noise 1.2-V core supply to image signal processors during high-speed burst capture, where transient response and PSRR matter. IC Role / Device Role / Timing Role: Channel 1 operates in forced PWM mode (via MODE/DATA = VIN) to suppress switching frequency harmonics interfering with analog imaging paths. Use Value: Fixed 2.25-MHz operation enables predictable EMI filtering; ±1% output accuracy prevents ISP clock jitter; 170-μs startup meets fast wake-from-sleep timing. |
Use Scenario: Powers TI C5000/C6000-series DSPs needing dual-rail support: 1.2 V for CPU core and 3.3 V for external memory interface. IC Role / Device Role / Timing Role: Independent EN1/EN2 pins allow staggered power-up to limit inrush current; 180° phase alignment reduces peak input demand during simultaneous load steps. Use Value: 400-mA/600-mA rating covers full DSP + memory load; VSON-10 package fits tight camera module layouts; thermal resistance (RθJA = 45.9°C/W) sustains continuous operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62403DRCT | VOUT1 = 1.575 V / 1.9 V (DEF_1-selectable); VOUT2 = 2.8 V fixed - different voltage pairing | Better suited for mixed-core+GPU SoCs requiring 1.575-V GPU rail and 2.8-V memory interface | Select when system requires 1.575-V/2.8-V combination instead of 1.2-V/3.3-V; same pinout and features |
| TPS62401DRCT | VOUT1 = 1.575 V / 1.1 V; VOUT2 = 1.8 V fixed - lower second rail optimized for core+peripheral partitioning | Ideal for OMAP™-based PDAs where 1.8-V I/O matches legacy interface standards | Choose if 1.8-V rail aligns with existing peripheral voltage plan; identical enable/control architecture and layout compatibility |
Compared with TPS62402DRCTG4, TPS62403DRCT offers higher VOUT2 (2.8 V vs 3.3 V) but lacks 3.3-V compatibility for modern memory interfaces, while TPS62401DRCT provides 1.8-V VOUT2 better suited for older I/O standards but insufficient for 3.3-V NAND or SDIO. Only TPS62402DRCTG4 delivers the precise 1.2-V/3.3-V pair required for contemporary low-power application processors with 3.3-V peripheral support.
Availability
TPS62402DRCTG4 is available at Aetrix Electronics and suitable for smartphone application processor core supplies, portable media player I/O rails, digital camera ISP cores, and low-power DSP subsystems requiring stable component supply across production lifecycles.
Supply support for TPS62402DRCTG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in power management ICs for portable and industrial applications.
The TPS6240x product line was designed specifically for battery-powered portable electronics requiring dual, independently controllable DC-DC rails with high efficiency, small solution size, and dynamic voltage scaling capability.
FAQ
What is the default output voltage configuration of the TPS62402DRCTG4?
The TPS62402DRCTG4 has two factory-configured output voltages: Channel 1 (VOUT1) defaults to 1.2 V when DEF_1 is pulled low, and Channel 2 (VOUT2) is fixed at 3.3 V with ADJ2 connected directly to the output. This pairing targets application processors needing scalable core voltage and standard 3.3-V I/O support. No external feedback resistors are required for either rail.
How does the MODE/DATA pin affect TPS62402DRCTG4 operation?
The MODE/DATA pin on the TPS62402DRCTG4 serves dual functions: when pulled low (GND), it enables automatic PFM/PWM mode transition for maximum light-load efficiency; when pulled high (VIN), it forces fixed-frequency PWM operation across all loads for predictable EMI filtering. It also acts as the bidirectional EasyScale™ serial interface for runtime output voltage updates without additional pins.
Can the TPS62402DRCTG4 support independent power sequencing for its two channels?
Yes, the TPS62402DRCTG4 supports fully independent power sequencing via dedicated enable pins: EN1 controls Channel 1 (1.2-V core rail) and EN2 controls Channel 2 (3.3-V I/O rail). This allows staggered startup to limit inrush current, selective shutdown of peripherals during sleep, and fault isolation - critical for complex portable SoC power architectures.
What package type and thermal characteristics does the TPS62402DRCTG4 use?
The TPS62402DRCTG4 uses a 10-pin VSON package (3.00 mm × 3.00 mm) with an exposed PowerPAD™ thermal pad. Its junction-to-ambient thermal resistance is 45.9°C/W, and junction-to-board resistance is 20.4°C/W. Proper soldering of the PowerPAD™ to a large PCB ground plane is mandatory to maintain safe junction temperatures at full 400-mA/600-mA load.
Is the TPS62402DRCTG4 compatible with 1.8-V logic-level control signals?
Yes, the TPS62402DRCTG4 accepts 1.8-V logic levels on its digital inputs: EN1, EN2, DEF_1, and MODE/DATA all specify VIH(min) = 1.2 V and VIL(max) = 0.4 V, making them compatible with 1.8-V GPIOs from modern application processors and microcontrollers without level-shifting circuitry.
TPS62402DRCTG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Programmable (Fixed)
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 1.2V, 1.8V (3.3V)
- Voltage - Output (Max):
- -
- Current - Output:
- 400mA, 600mA
- Frequency - Switching:
- 2.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSON (3x3)
TPS62402DRCTG4 FAQ
1.How can I place an order for TPS62402DRCTG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS62402DRCTG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS62402DRCTG4 reliable?
The price and inventory of TPS62402DRCTG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS62402DRCTG4 is usually 5 days.
3.What payment methods are accepted for TPS62402DRCTG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS62402DRCTG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS62402DRCTG4?
TPS62402DRCTG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS62402DRCTG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS62402DRCTG4?
For technical support, including TPS62402DRCTG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS62402DRCTG4 requirements.
6.How does Aetrix verify that TPS62402DRCTG4 is sourced from the original manufacturer or authorized distributors?
All TPS62402DRCTG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS62402DRCTG4 meets industry standards.
7.What is the process for return or replacement of TPS62402DRCTG4?
All TPS62402DRCTG4 units undergo pre-shipment inspection (PSI). If there is an issue with TPS62402DRCTG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS62402DRCTG4 part is unused and in its original packaging.
Return procedure for TPS62402DRCTG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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