My Inquiry
My Account
Texas Instruments TPS62403DRCR
- Part No.:
- TPS62403DRCR
- Manufacturer:
- Texas Instruments
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TPS62403DRCR.pdf
- Description:
- IC REG BUCK PROG/2.8V DL 10VSON
- Quantity:
- Payment:
- Shipping:
Inventory:3,280
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS62403DRCR from Texas Instruments is a dual synchronous step-down DC-DC converter IC optimized for battery-powered portable electronics. It delivers 400 mA on Channel 1 (default 1.575 V) and 600 mA on Channel 2 (default 2.8 V), operates from 2.5 V to 6 V input, uses fixed 2.25 MHz switching frequency, and integrates 180° out-of-phase operation to reduce input ripple - deployed in OMAP™ processor power rails and smart phone baseband subsystems.
For engineers reviewing the TPS62403DRCR datasheet, TPS62403DRCR pinout, TPS62403DRCR application, or TPS62403DRCR equivalent, key selection considerations include dual-rail dynamic voltage scaling via DEF_1 pin, EasyScale™ one-wire interface support, ±1% output accuracy in PWM mode, 32 μA typical quiescent current with both converters active, and compatibility with 2.2 μH inductors and ceramic output capacitors in space-constrained designs.
Technical Context
The TPS62403DRCR implements two independent voltage-mode synchronous buck regulators sharing a single 2.25 MHz oscillator with 180° phase shift between channels. Each channel features integrated P-channel and N-channel MOSFETs with 280 mΩ/200 mΩ typical RDS(on), internal compensation, and separate enable (EN1/EN2) and feedback (FB1/ADJ2) paths.
It supports three operational modes: automatic Power Save Mode (PFM at light load, PWM at heavy load), forced PWM mode (via MODE/DATA = high), and shutdown (EN1 = EN2 = low, 1.2 μA ISD). Output voltage selection for Channel 1 is digital via DEF_1 pin (1.575 V low / 2.8 V high), while Channel 2 is fixed at 2.8 V with ADJ2 tied directly to VOUT2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 2.5 V to 6 V - supports single-cell Li-ion (3.0–4.2 V) and regulated 3.3 V/5 V rails without external LDO pre-regulation. |
| Output 1 (VOUT1) | 1.575 V (DEF_1 = low) or 2.8 V (DEF_1 = high), 400 mA max - pin-selectable for dynamic voltage scaling of core logic or memory interfaces. |
| Output 2 (VOUT2) | Fixed 2.8 V, 600 mA max - dedicated rail for I/O, analog front-end, or RF biasing with no external resistor network required. |
| Switching Frequency | 2.25 MHz (±12.5%) - enables use of compact 2.2 μH inductors and low-ESR ceramic capacitors; reduces solution footprint vs lower-frequency converters. |
| Quiescent Current | 32 μA typical (both converters enabled, no load, PFM mode) - extends battery runtime in standby and low-activity states. |
| Output Accuracy | ±1% in PWM mode (VIN = 2.5–6.0 V, 0–400/600 mA load) - ensures stable core voltage under process/temperature variation for reliable SoC operation. |
| Shutdown Current | 1.2 μA typical - minimizes battery drain during system sleep or power-off states. |
Pinout & Package
TPS62403DRCR is housed in a thermally enhanced 10-pin VSON package (3.0 mm × 3.0 mm, 0.5 mm pitch) with exposed PowerPAD™ for improved thermal dissipation (RθJA = 45.9 °C/W). The package is RoHS-compliant and moisture-sensitive level 2a per J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - ADJ2 | Converter 2 feedback reference | Must be connected directly to VOUT2 (2.8 V); not used for external resistor programming in fixed-output versions. |
| 2 - MODE/DATA | Mode control & serial interface | Low = auto PFM/PWM mode; high = forced PWM; also serves as EasyScale™ data line for runtime VOUT adjustment. |
| 3 - VIN | Main power input | Supplies both converters; accepts 2.5–6 V; requires local 10 μF ceramic decoupling near pin. |
| 4 - FB1 | Converter 1 feedback sense | Direct connection to VOUT1; internal resistor divider sets regulation point - no external resistors needed for fixed outputs. |
| 5 - DEF_1 | Channel 1 output select | Digital input: low = 1.575 V, high = 2.8 V; enables hardware-based DVS without software or serial interface. |
| 6 - SW1 | Channel 1 power switch node | Connects to 2.2 μH inductor; carries high di/dt switching current - requires short, low-inductance PCB trace. |
| 7 - EN1 | Channel 1 enable | Active-high; controls startup/shutdown of Converter 1 independently; must not float (pull down if unused). |
| 8 - GND | Power and signal ground | Common return for both converters; ties to PowerPAD™ for thermal and EMI performance. |
| 9 - EN2 | Channel 2 enable | Active-high; independent control of Converter 2; allows staggered power-up or rail sequencing. |
| 10 - SW2 | Channel 2 power switch node | Connects to second 2.2 μH inductor; 180° phase shift vs SW1 reduces input capacitor RMS current by ~30%. |
Key Features
| Feature | Design Value |
|---|---|
| 180° out-of-phase operation | Reduces input ripple current amplitude and RMS value, enabling smaller input bulk capacitance and lower EMI filtering cost. |
| Pin-selectable dual VOUT1 options | Hardware-configurable 1.575 V / 2.8 V outputs eliminate need for firmware or serial interface during boot or fault recovery. |
| EasyScale™ one-pin serial interface | Allows real-time reconfiguration of both output voltages using only MODE/DATA pin - no additional GPIO or I²C lines required. |
| 100% duty cycle capability | Enables dropout operation down to VOUT + ~100 mV (e.g., 2.8 V out at 2.9 V in), critical for end-of-battery-life operation. |
| Integrated short-circuit protection | Auto-recovering current limiting (0.85–1.15 A) on both channels prevents damage during board-level test or transient faults. |
Applications
| Smartphone Application Processor Core Rail | Portable Media Player Audio Codec Bias |
|---|---|
|
Use Scenario: Powers ARM Cortex-A8/A9 cores in OMAP™-based smartphones requiring dynamic voltage scaling across performance states. IC Role / Device Role / Timing Role: Dual-rail buck regulator delivering 1.575 V (LPM) and 2.8 V (active) with hardware-selectable DEF_1 and synchronized switching. Use Value: Enables >20% reduction in active-mode power vs fixed-voltage solutions; 180° phase shift lowers input capacitor count from two 10 μF to one 10 μF + one 4.7 μF. |
Use Scenario: Supplies clean, low-noise 2.8 V bias to stereo audio DAC/ADC and Class AB headphone amplifier in MP3 players. IC Role / Device Role / Timing Role: Fixed 2.8 V Channel 2 acts as primary analog rail; Channel 1 (1.575 V) powers low-power DSP co-processor. Use Value: Forced PWM mode (MODE/DATA = high) eliminates audible switching noise; ±1% accuracy maintains THD+N < 0.01% across temperature. |
| PDAs with Dual-Voltage Memory Interface | Low-Power DSP + RF Front-End System |
|
Use Scenario: Powers DDR SDRAM (1.8 V) and application processor (1.2 V) in legacy PDA platforms using discrete voltage selection. IC Role / Device Role / Timing Role: TPS62403DRCR Channel 1 (1.575 V default) configured via DEF_1 and EasyScale™ to generate 1.2 V/1.8 V; Channel 2 supplies 2.8 V RF bias. Use Value: Eliminates need for external level translators or second PMIC; pin-selectable VOUT1 reduces BOM count by one resistor network. |
Use Scenario: Powers TI C55x DSP core (1.2 V) and 2.4 GHz transceiver IC (2.8 V) in Bluetooth/Wi-Fi combo modules. IC Role / Device Role / Timing Role: Channel 1 delivers 1.575 V (scaled to 1.2 V via EasyScale™) to DSP; Channel 2 provides stable 2.8 V to PA driver stage. Use Value: 32 μA quiescent current extends shelf life in always-on IoT nodes; 100% duty cycle sustains 2.8 V output down to 2.9 V battery voltage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62401DRCR | Fixed 1.575 V / 1.8 V outputs; no DEF_1 voltage option; identical package and pinout. | Limited to baseband + memory rail pairs (e.g., 1.575 V CPU + 1.8 V DDR); lacks 2.8 V capability for RF bias. | Select when system requires only 1.575 V/1.8 V rails and does not need hardware-selectable higher VOUT1. |
| TPS62404DRCR | Fixed 1.2 V / 3.3 V outputs; same 2.25 MHz frequency and 400/600 mA ratings. | Targets low-voltage microcontrollers (1.2 V) and 3.3 V peripherals (USB PHY, SDIO); incompatible with 2.8 V RF loads. | Choose for mixed-signal MCU systems needing 1.2 V core + 3.3 V I/O, where 2.8 V is unnecessary. |
Compared with TPS62401DRCR and TPS62404DRCR, the TPS62403DRCR uniquely supports 2.8 V on Channel 2 - essential for powering modern RF front-ends - while retaining pin-selectable 1.575 V/2.8 V on Channel 1 for flexible core/I/O partitioning without firmware dependency.
Availability
TPS62403DRCR is available at Aetrix Electronics and suitable for smartphone power management, OMAP™ processor supply, and portable media player design requiring stable component supply, long-term lifecycle support, and full traceability.
Supply support for TPS62403DRCR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with over 90 years of innovation in energy-efficient electronics.
The TPS6240x family was designed specifically for space-constrained, battery-operated portable devices requiring dual independent DC-DC rails with dynamic voltage scaling, low quiescent current, and minimal external components.
FAQ
What are the default output voltages of TPS62403DRCR?
The TPS62403DRCR has two fixed output voltages: Channel 1 defaults to 1.575 V when DEF_1 is low, or 2.8 V when DEF_1 is high; Channel 2 is fixed at 2.8 V. These values are factory-programmed and require no external resistors - ADJ2 must be tied directly to VOUT2, and FB1 connects directly to VOUT1.
Does TPS62403DRCR support dynamic voltage scaling without a microcontroller?
Yes. TPS62403DRCR supports hardware-based dynamic voltage scaling via the DEF_1 pin: pulling it low selects 1.575 V for VOUT1, and pulling it high selects 2.8 V. This enables voltage changes at boot or during system reset without firmware or serial communication - a key advantage over purely software-controlled alternatives.
Can TPS62403DRCR operate with only one channel enabled?
Yes. TPS62403DRCR supports independent channel control: EN1 enables/disables Channel 1 (1.575 V / 2.8 V), and EN2 controls Channel 2 (2.8 V). Either can be held low to disable its respective converter while the other remains active - useful for power sequencing, rail isolation, or partial-system sleep modes.
What inductor value is recommended for TPS62403DRCR?
Texas Instruments specifies 2.2 μH for both channels in the TPS62403DRCR datasheet (SLVS681F). This value is optimized for 2.25 MHz operation, 400/600 mA output current, and minimal size - paired with 10 μF ceramic input and 20 μF ceramic output capacitors for stable regulation and low output ripple.
Is TPS62403DRCR compatible with forced PWM mode for noise-sensitive applications?
Yes. Driving the MODE/DATA pin high forces both TPS62403DRCR channels into fixed-frequency PWM mode across all load conditions. This eliminates variable-frequency PFM noise, simplifies EMI filtering, and ensures predictable switching harmonics - ideal for audio, RF, or precision analog circuits sharing the same PCB.
TPS62403DRCR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Programmable (Fixed)
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 1.1V, 1.575V (2.8V)
- Voltage - Output (Max):
- -
- Current - Output:
- 400mA, 600mA
- Frequency - Switching:
- 2.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSON (3x3)
TPS62403DRCR FAQ
1.How can I place an order for TPS62403DRCR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS62403DRCR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS62403DRCR reliable?
The price and inventory of TPS62403DRCR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS62403DRCR is usually 5 days.
3.What payment methods are accepted for TPS62403DRCR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS62403DRCR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS62403DRCR?
TPS62403DRCR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS62403DRCR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS62403DRCR?
For technical support, including TPS62403DRCR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS62403DRCR requirements.
6.How does Aetrix verify that TPS62403DRCR is sourced from the original manufacturer or authorized distributors?
All TPS62403DRCR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS62403DRCR meets industry standards.
7.What is the process for return or replacement of TPS62403DRCR?
All TPS62403DRCR units undergo pre-shipment inspection (PSI). If there is an issue with TPS62403DRCR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS62403DRCR part is unused and in its original packaging.
Return procedure for TPS62403DRCR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS62403DRCR Tags
-
TPS562201DDCR
Texas Instruments
-
MC34063ABD-TR
STMicroelectronics
-
TPS561201DDCR
Texas Instruments
-
MC33063ADR
Texas Instruments
-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments
-
AP3012KTR-G1
Diodes Incorporated
-
TLV61048DBVR
Texas Instruments
-
AZ34063UMTR-G1
Diodes Incorporated
-
TPS562200DDCR
Texas Instruments
-
AP62300TWU-7
Diodes Incorporated
-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
