Texas Instruments TPS62404DRCR
- Part No.:
- TPS62404DRCR
- Manufacturer:
- Texas Instruments
- Package:
- 10-VFDFN Exposed Pad
- Datasheet:
-
TPS62404DRCR.pdf
- Description:
- IC REG BUCK PROG/3.3V DL 10VSON
- Quantity:
- Payment:

- Shipping:

Inventory:4,917
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS62404DRCR from Texas Instruments is a dual synchronous step-down DC-DC converter IC optimized for battery-powered portable systems, delivering 400 mA on Channel 1 (VOUT1 = 1.2 V default) and 600 mA on Channel 2 (VOUT2 = 3.3 V default), operating from 2.5 V to 6 V input with 2.25-MHz fixed-frequency PWM switching and 180° out-of-phase operation to reduce input ripple.
For engineers reviewing the TPS62404DRCR datasheet, TPS62404DRCR pinout, TPS62404DRCR application, or TPS62404DRCR equivalent, this device supports dynamic voltage scaling via DEF_1 pin selection and EasyScale™ one-wire interface, features ±1% output voltage accuracy in PWM mode, 32-μA typical quiescent current for both converters, and operates in a space-constrained 3-mm × 3-mm VSON-10 package.
Technical Context
The TPS62404DRCR integrates two independent synchronous buck regulators sharing a single 2.25-MHz oscillator with 180° phase shift-reducing input RMS current and easing EMI filtering. Each channel uses voltage-mode control with input voltage feed-forward for fast transient response and stable regulation across 0.6 V–VIN output range.
Converter 1 defaults to 1.2 V (DEF_1 = low) and Converter 2 to 3.3 V; both support real-time reconfiguration via EasyScale™ serial interface on MODE/DATA pin. Power Save Mode enables PFM operation at light loads, while forced PWM mode (MODE/DATA = high) ensures constant frequency for noise-sensitive applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 2.5 V to 6 V - supports single-cell Li-ion (3.0–4.2 V) and regulated 3.3-V/5-V rails without external LDO pre-regulation. |
| VOUT1 Default | 1.2 V (DEF_1 = low) - matches core voltage requirements of OMAP™ processors and low-power DSPs. |
| VOUT2 Default | 3.3 V (DEF_1 = low) - supplies I/O, memory, or peripheral rails in portable media players and digital radios. |
| Output Current | 400 mA (CH1), 600 mA (CH2) - sufficient for dual-rail SoC power domains with margin for peak transients. |
| Switching Frequency | 2.25 MHz (±12.5%) - enables use of compact 2.2-μH inductors and 10-μF ceramic capacitors for minimal PCB footprint. |
| Quiescent Current | 32 μA (both converters enabled, PFM mode) - extends battery life in always-on subsystems like real-time clocks or sensor hubs. |
| Output Accuracy | ±1% in PWM mode - ensures reliable logic-level compliance for 1.2-V core and 3.3-V I/O interfaces under full load and temperature. |
Pinout & Package
TPS62404DRCR is housed in a thermally enhanced 10-pin VSON package (3.0 mm × 3.0 mm, 0.5-mm pitch) with exposed PowerPAD™ for improved thermal dissipation (RθJA = 45.9°C/W). Pin 8 (GND) connects directly to the PowerPAD™, requiring solid thermal vias to internal ground planes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DEF_1 (Pin 5) | Digital select input for VOUT1 | Low = 1.2 V default; high = 1.1 V default - enables hardware-selectable core voltage scaling without firmware intervention. |
| EN_1 (Pin 7) | Enable control for Converter 1 | Active-high; independent startup/shutdown of CH1 allows staggered power sequencing for SoC domain isolation. |
| EN_2 (Pin 9) | Enable control for Converter 2 | Active-high; decouples I/O rail enable timing from core rail, supporting flexible power-up/down sequences. |
| FB1 (Pin 4) | Feedback sense for VOUT1 | Direct connection to VOUT1 node - eliminates external resistor divider, simplifying layout and improving regulation accuracy. |
| ADJ2 (Pin 1) | Adjust input for VOUT2 | Must be shorted to VOUT2 in fixed-output mode - disables external programming and activates internal 3.3-V reference network. |
| MODE/DATA (Pin 2) | Mode control & serial interface | Configures PFM/PWM operation or accepts EasyScale™ commands - enables runtime voltage updates without dedicated I²C lines. |
| SW1 (Pin 6), SW2 (Pin 10) | Power switch outputs | Connect to external 2.2-μH inductors - integrated 280-mΩ P-MOS and 200-mΩ N-MOS switches minimize conduction loss. |
| VIN (Pin 3) | Main input supply | Accepts 2.5–6 V with integrated UVLO (1.5–2.35 V threshold) - prevents brownout operation and protects Li-ion cells from over-discharge. |
| GND (Pin 8) | Power and signal ground | Common return for both converters and PowerPAD™ - requires low-impedance connection to minimize ground bounce during switching transitions. |
Key Features
| Feature | Design Value |
|---|---|
| 180° out-of-phase operation | Reduces input capacitor RMS current by ~30%, allowing smaller 10-μF X5R ceramics instead of larger bulk electrolytics. |
| EasyScale™ one-pin interface | Enables dynamic VOUT1/VOUT2 adjustment via MODE/DATA pin - eliminates need for I²C/SPI controllers in space-constrained designs. |
| 100% duty cycle capability | Maintains regulation down to VOUT = VIN − 0.5 V (for VOUT > 2 V) - supports ultra-low dropout operation during battery sag conditions. |
| Integrated soft-start | Controls VOUT ramp time to 750 μs (5–95%) - prevents inrush current spikes that could destabilize shared input rails. |
| Thermal shutdown with hysteresis | Triggers at 150°C junction temperature with 20°C hysteresis - protects against sustained overload or poor heatsinking without oscillation. |
Applications
| Smartphone Application Processor Core | Portable Media Player I/O Rail |
|---|---|
Use Scenario: Powers ARM Cortex-A8/A9 core in OMAP™-based smartphones during active video decode and UI rendering. IC Role / Device Role / Timing Role: Dual-rail PMIC providing dynamically scaled 1.2-V core and fixed 3.3-V I/O from single Li-ion cell. Use Value: DEF_1 pin selects 1.2-V core voltage; EasyScale™ adjusts VOUT1 in real time to match CPU load states, reducing average power by up to 22%. |
Use Scenario: Supplies 3.3-V interface for SD card, USB PHY, and display controller in flash-based audio/video players. IC Role / Device Role / Timing Role: Secondary buck regulator delivering stable 3.3-V rail synchronized 180° out-of-phase with core rail to minimize input ripple. Use Value: 2.25-MHz switching enables use of 2.2-μH shielded inductor and 10-μF ceramic output cap - cuts solution size by 40% vs. 500-kHz alternatives. |
| Digital Radio Baseband SoC | Low-Power DSP Subsystem |
Use Scenario: Powers multi-core baseband processor in DAB/DVB-H receivers with burst-mode RF transmission. IC Role / Device Role / Timing Role: Dual-channel converter delivering 1.2-V core and 3.3-V analog/RF interface with independent EN_1/EN_2 control. Use Value: Independent enable pins allow core shutdown during RF sleep cycles while maintaining 3.3-V bias for crystal oscillator and LNA - reduces system standby current to <5 μA. |
Use Scenario: Supplies TI C55x/C674x DSP cores and peripherals in battery-operated acoustic sensors and voice recorders. IC Role / Device Role / Timing Role: Synchronous buck pair with 180° phase shift feeding DSP core (1.2 V) and ADC/DAC interface (3.3 V). Use Value: 32-μA quiescent current in PFM mode extends battery life to >120 hours in always-listening mode; ±1% PWM accuracy ensures consistent ADC reference stability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62403DRCR | Default VOUT1 = 1.575 V, VOUT2 = 2.8 V - higher core voltage, lower I/O rail. | Suitable for legacy OMAP-L138 or DaVinci™ platforms requiring 1.575-V core and 2.8-V memory interface. | Select when matching existing 1.575-V/2.8-V reference designs; not drop-in due to different default outputs and register mapping. |
| TPS62401DRCR | Default VOUT1 = 1.575 V, VOUT2 = 1.8 V - lower I/O rail, same core voltage as TPS62403. | Optimized for smart phone application processors with 1.575-V core and 1.8-V LPDDR2 I/O. | Choose for 1.575-V/1.8-V dual-rail systems; shares pinout but requires DEF_1 and ADJ2 reconfiguration to match TPS62404's 1.2-V/3.3-V defaults. |
Compared with TPS62403DRCR and TPS62401DRCR, the TPS62404DRCR provides the only 1.2-V/3.3-V fixed-output combination in the family, making it uniquely suited for newer OMAP4/5 SoCs and portable media players requiring tighter core voltage margins and standard 3.3-V peripheral compatibility.
Availability
TPS62404DRCR is available at Aetrix Electronics and suitable for smartphone application processor core supplies, portable media player I/O rails, digital radio baseband SoCs, low-power DSP subsystems, and OMAP™ platform development requiring stable component supply across production lifecycles.
Supply support for TPS62404DRCR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC-DC conversion for portable and industrial applications.
The TPS6240x product line was designed specifically for battery-powered portable electronics requiring dual independent buck regulators in ultra-small packages, emphasizing efficiency across light-to-heavy load ranges and seamless integration with TI's OMAP™ and DaVinci™ processor platforms.
FAQ
What is the default output voltage configuration of the TPS62404DRCR?
The TPS62404DRCR has fixed default output voltages set by internal resistor networks: Channel 1 (VOUT1) delivers 1.2 V when DEF_1 is pulled low, and Channel 2 (VOUT2) delivers 3.3 V regardless of DEF_1 state. These defaults are confirmed in the Device Options table of the SLVS681F datasheet and require no external feedback resistors - ADJ2 must be shorted to VOUT2 and FB1 to VOUT1 for proper operation.
Does the TPS62404DRCR support dynamic voltage scaling (DVS)?
Yes, the TPS62404DRCR supports hardware-based and software-based DVS. Hardware DVS is implemented via the DEF_1 pin (selecting between 1.2 V and 1.1 V for VOUT1), while software DVS uses the EasyScale™ one-pin serial interface on MODE/DATA to reprogram both VOUT1 and VOUT2 registers during operation - enabling real-time adaptation to CPU load states without interrupting system function.
What package type and thermal characteristics does the TPS62404DRCR use?
The TPS62404DRCR is packaged in a 10-pin VSON (DRC) case measuring 3.0 mm × 3.0 mm with an exposed PowerPAD™. Its thermal resistance is RθJA = 45.9°C/W (junction-to-ambient) and RθJB = 20.4°C/W (junction-to-board), verified per JEDEC JESD51 standards. Proper PCB layout - including ≥4 thermal vias under the PowerPAD™ connected to a solid inner ground plane - is required to sustain 600-mA continuous output on Channel 2.
Can the TPS62404DRCR operate with only one channel enabled?
Yes, the TPS62404DRCR supports independent channel control: EN_1 (Pin 7) enables/disables Channel 1 and EN_2 (Pin 9) controls Channel 2. Either converter can operate standalone while the other remains in shutdown (1.2-μA quiescent current), enabling power sequencing, domain isolation, and partial-system wake-up - critical for low-power audio codecs and sensor hubs where only one rail is active at a time.
What is the minimum input voltage required for the TPS62404DRCR to regulate 3.3 V on Channel 2?
To regulate 3.3 V on Channel 2, the TPS62404DRCR requires VIN ≥ 3.8 V under typical conditions, as specified in the Electrical Characteristics table footnote (8): "For VOUT > 2 V, VIN min = VOUT + 0.5 V". This accounts for MOSFET RDS(ON), inductor DCR, and control loop headroom. At VIN = 3.6 V, VOUT2 will droop below 3.3 V under load; operation at 3.3 V output is only guaranteed above 3.8 V input.
TPS62404DRCR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 10-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Programmable (Fixed)
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 6V
- Voltage - Output (Min/Fixed):
- 1.2V, 1.9V (3.3V)
- Voltage - Output (Max):
- -
- Current - Output:
- 400mA, 600mA
- Frequency - Switching:
- 2.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-VSON (3x3)
TPS62404DRCR FAQ
1.How can I place an order for TPS62404DRCR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS62404DRCR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS62404DRCR reliable?
The price and inventory of TPS62404DRCR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS62404DRCR is usually 5 days.
3.What payment methods are accepted for TPS62404DRCR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS62404DRCR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS62404DRCR?
TPS62404DRCR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS62404DRCR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS62404DRCR?
For technical support, including TPS62404DRCR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS62404DRCR requirements.
6.How does Aetrix verify that TPS62404DRCR is sourced from the original manufacturer or authorized distributors?
All TPS62404DRCR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS62404DRCR meets industry standards.
7.What is the process for return or replacement of TPS62404DRCR?
All TPS62404DRCR units undergo pre-shipment inspection (PSI). If there is an issue with TPS62404DRCR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS62404DRCR part is unused and in its original packaging.
Return procedure for TPS62404DRCR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS62404DRCR Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

