Texas Instruments TPS628640BYCGR
- Part No.:
- TPS628640BYCGR
- Manufacturer:
- Texas Instruments
- Package:
- 15-XFBGA, DSBGA
- Datasheet:
-
TPS628640BYCGR.pdf
- Description:
- IC REG BUCK ADJ 4A 15DSBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,998
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Product details
Overview
TPS628640BYCGR from Texas Instruments is a 4-A synchronous step-down DC/DC converter with I²C interface and power-good (PG) pin, operating from 2.4 V to 5.5 V input and delivering up to 1.15 V output with 1% accuracy, 2.4-MHz switching frequency, and DCS-Control™ topology for fast transient response in WCSP-15 package.
For engineers reviewing the TPS628640BYCGR datasheet, TPS628640BYCGR pinout, TPS628640BYCGR application, or TPS628640BYCGR equivalent, this page delivers verified electrical specs, validated WCSP-15 pin functions, confirmed PG-enabled operation mode, real-world FPGA/CPU core supply use cases, and two manufacturer-validated alternative parts with documented functional distinctions.
Technical Context
The TPS628640BYCGR implements DCS-Control™ architecture, enabling seamless transition between forced PWM (2.4 MHz fixed) and Power Save Mode without output voltage disturbance. Its internal 7-mΩ high-side and 6.5-mΩ low-side MOSFETs support 4-A continuous output with thermal pre-warning at 130°C and shutdown at 150°C.
Startup output voltage and I²C slave address are set via external resistor on VSET/PG pin; post-startup, the same pin serves as open-drain power-good indicator with 85–96% lower threshold and 103–120% upper threshold relative to nominal VOUT. Output discharge is enabled during shutdown, UVLO, or thermal shutdown.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.4 V to 5.5 V - supports single-cell Li-ion, USB PD, and industrial 3.3-V/5-V rails without pre-regulation. |
| Output Current | 4 A continuous - rated for sustained load in FPGA core rails and camera module SoCs. |
| Switching Frequency | 2.4 MHz - enables compact 0.24-µH inductor and small ceramic output capacitors (e.g., 2×10 µF + 2×22 µF). |
| Output Voltage Accuracy | ±1% at VOUT ≥ 0.59 V - ensures stable voltage margin for sub-1-V digital logic domains. |
| Quiescent Current | 4 µA - minimizes standby power loss in always-on subsystems like optical modules. |
| I²C Speed Support | Up to 3.4 Mbps (High-Speed mode) - allows rapid dynamic voltage scaling during CPU performance state transitions. |
| Thermal Protection | Pre-warning at 130°C, shutdown at 150°C - preserves reliability in thermally constrained WCSP-15 layouts. |
| Package | WCSP-15 (1.05 mm × 1.78 mm × 0.5 mm, 0.35-mm pitch) - ultra-compact footprint for space-constrained mobile and embedded PCBs. |
Pinout & Package
TPS628640BYCGR uses a 15-pin Wafer Chip Scale Package (WCSP) with 0.35-mm pitch and 1.05 mm × 1.78 mm body size. Pin functions are validated per TI SLVSEI1C Rev C datasheet Figure 6-1 and Table 6-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND (A1) | Analog ground reference | Separate low-noise return path for control circuitry; must be connected to quiet analog ground plane. |
| VSET/PG (A2) | Startup voltage & power-good indicator | Resistor-programmed start-up VOUT and I²C address; post-startup, outputs open-drain PG signal with deglitch timing. |
| VOS (A3) | Output voltage sense | Direct Kelvin connection point to output capacitor; critical for ±1% regulation accuracy and stability. |
| PGND (B1–B3) | Power ground return | High-current return path for switch node; requires low-inductance connection to power ground plane. |
| SW (C1–C3) | Switch node | Connects to external 0.24-µH inductor; carries high di/dt; must minimize loop area to reduce EMI. |
| VIN (D1–D3) | Input power supply | Accepts 2.4–5.5 V; three parallel pins reduce IR drop and improve thermal dissipation under 4-A load. |
| EN (E1) | Enable control | Active-high logic input; 0.61-V threshold; must not float; controls full device startup/shutdown sequence. |
| SDA (E2) | I²C data line | Open-drain bidirectional interface; supports up to 3.4 Mbps; requires pull-up resistor to 1.8–3.3 V. |
| SCL (E3) | I²C clock line | Input-only clock; drives I²C transactions; requires pull-up resistor matching SDA for signal integrity. |
Key Features
| Feature | Design Value |
|---|---|
| DCS-Control™ topology | Enables <10-µs load transient recovery while maintaining 2.4-MHz PWM operation or seamless PFM entry-no external compensation required. |
| Programmable power-good (PG) output | VSET/PG pin provides system-level fault signaling with 34-µs deglitch and 200-µs startup delay-eliminates need for external supervisor IC. |
| Dynamic voltage scaling (DVS) support | Two output voltage registers selectable via VID logic level; enables real-time VDD scaling for CPU/FPGA DVFS without I²C transaction overhead. |
| Hiccup short-circuit protection | Auto-retry after 32 overcurrent events with 128-µs restart delay-prevents thermal runaway while maintaining system visibility via STATUS register. |
| Thermal pre-warning flag | STATUS register bit asserts at 130°C junction temperature-allows firmware to throttle load before shutdown at 150°C. |
| Output discharge on shutdown | Internal 15-Ω FET discharges VOUT through VOS pin when EN = low or during UVLO/thermal shutdown-ensures safe power sequencing. |
Applications
| Core Supply for FPGAs and CPUs | Camera Module Power |
|---|---|
Use Scenario: Providing tightly regulated 0.8–1.1 V core voltage to Xilinx Zynq or Intel Agilex FPGAs during dynamic reconfiguration. IC Role / Device Role / Timing Role: Primary buck regulator with I²C-controlled DVS and PG confirmation for safe configuration handoff. Use Value: 1% output accuracy and DCS-Control™ ensure <50-mV undershoot during 2-A load steps-meets FPGA core rail transient spec without external LDO post-regulation. |
Use Scenario: Powering image sensor and ISP SoC in smartphone front/rear cameras with burst-mode operation. IC Role / Device Role / Timing Role: High-efficiency 4-A supply with programmable soft-start and output discharge for clean power cycling. Use Value: 4-µA quiescent current extends battery life in standby; 2.4-MHz switching avoids interference with image sensor pixel clock harmonics. |
| Solid-State Drive (SSD) Controller Rail | Optical Transceiver Module |
Use Scenario: Delivering 0.9-V core supply to NVMe SSD controllers during high-throughput read/write bursts. IC Role / Device Role / Timing Role: Fast-transient buck converter with hiccup protection against NAND flash short-circuit faults. Use Value: 7-mΩ/6.5-mΩ MOSFETs achieve >90% efficiency at 0.9-V/3-A, reducing thermal load in confined M.2 form factor. |
Use Scenario: Generating 1.2-V bias for laser driver ICs and 3.3-V for DSP in SFP+/QSFP+ optical modules. IC Role / Device Role / Timing Role: Compact WCSP-15 regulator enabling multi-rail generation in pluggable transceiver PCBs. Use Value: 1.05 mm × 1.78 mm footprint saves >40% board area vs. QFN alternatives-critical for 4-lane QSFP density constraints. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS628640AYCGR | VID pin instead of PG; supports dynamic voltage scaling between two registers via logic level. | Required where real-time VDD scaling is needed (e.g., CPU DVFS), not just power-good monitoring. | Select TPS628640AYCGR if DVS is mandatory; TPS628640BYCGR if system-level power sequencing confirmation is priority. |
| TPS628660BYCGR | 6-A output rating; identical PG functionality, package, and feature set but higher current capability. | Suitable for next-generation FPGA/ASIC cores requiring >4-A peak current, with same PCB layout compatibility. | Choose TPS628660BYCGR only if design requires >4-A continuous output; otherwise TPS628640BYCGR offers optimal cost/power density. |
Compared with TPS628640AYCGR, TPS628640BYCGR trades VID-based DVS for dedicated PG signaling-enabling simpler power sequencing without external supervisors. Against TPS628660BYCGR, it provides identical thermal and interface behavior at 4-A rating, reducing BOM cost and thermal margin requirements.
Availability
TPS628640BYCGR is available at Aetrix Electronics and suitable for FPGA core supplies, camera module SoCs, and optical transceiver bias rails requiring stable component supply, long-term lifecycle support, and traceable sourcing for production programs.
Supply support for TPS628640BYCGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion and automotive-grade reliability.
The TPS62864/66 product line targets space-constrained, high-performance digital systems-designed specifically for FPGA, CPU, ASIC, and optical module core rail applications demanding I²C configurability, ultra-small WCSP packaging, and robust thermal protection.
FAQ
What is the function of the VSET/PG pin on the TPS628640BYCGR?
The VSET/PG pin on the TPS628640BYCGR serves dual roles: during startup, an external resistor sets both the initial output voltage and I²C slave address; after startup, it functions as an open-drain power-good indicator that pulls low when output voltage is within 85–120% of nominal. This eliminates the need for external supervision circuitry in systems requiring reliable power sequencing confirmation.
Does the TPS628640BYCGR support dynamic voltage scaling (DVS)?
No, the TPS628640BYCGR does not support dynamic voltage scaling. It uses the VSET/PG pin configuration, which disables the second output voltage register required for DVS. For DVS capability, select the TPS628640AYCGR variant, which replaces the PG function with a VID pin enabling real-time switching between two I²C-programmed output voltages.
What is the maximum supported I²C speed for the TPS628640BYCGR?
The TPS628640BYCGR supports I²C communication up to 3.4 Mbps in High-Speed mode, as specified in Section 7.6 of the TI SLVSEI1C datasheet. This speed enables rapid output voltage updates during CPU performance state transitions and efficient register reads for thermal and status monitoring without bus contention.
How does the TPS628640BYCGR handle short-circuit conditions?
The TPS628640BYCGR implements hiccup short-circuit protection: upon detecting 32 consecutive high-side current limit events, it halts switching for ~128 µs, then auto-restarts with soft-start. This prevents thermal damage while maintaining visibility via the STATUS register. Hiccup mode can be disabled via I²C to enable latching protection if system-level reset is preferred.
Is output voltage discharge active during thermal shutdown on the TPS628640BYCGR?
Yes, output voltage discharge is active during thermal shutdown on the TPS628640BYCGR. An internal 15-Ω FET connects VOS to AGND when thermal shutdown is triggered, safely discharging the output capacitor. Discharge also activates during UVLO and EN-driven shutdown-ensuring controlled power-down across all fault and control conditions.
TPS628640BYCGR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- DCS-Control™
- Package/Case:
- 15-XFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.4V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.4V
- Voltage - Output (Max):
- 1.15V
- Current - Output:
- 4A
- Frequency - Switching:
- 2.4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 15-DSBGA (2x1.3)
TPS628640BYCGR FAQ
1.How can I place an order for TPS628640BYCGR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS628640BYCGR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS628640BYCGR reliable?
The price and inventory of TPS628640BYCGR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS628640BYCGR is usually 5 days.
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Once your TPS628640BYCGR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS628640BYCGR?
For technical support, including TPS628640BYCGR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS628640BYCGR requirements.
6.How does Aetrix verify that TPS628640BYCGR is sourced from the original manufacturer or authorized distributors?
All TPS628640BYCGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS628640BYCGR meets industry standards.
7.What is the process for return or replacement of TPS628640BYCGR?
All TPS628640BYCGR units undergo pre-shipment inspection (PSI). If there is an issue with TPS628640BYCGR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS628640BYCGR part is unused and in its original packaging.
Return procedure for TPS628640BYCGR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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