Texas Instruments TPS628680ARQYR
- Part No.:
- TPS628680ARQYR
- Manufacturer:
- Texas Instruments
- Package:
- 9-PowerVFQFN
- Datasheet:
-
TPS628680ARQYR.pdf
- Description:
- IC REG BUCK ADJ 4A 9VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:908
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Product details
Overview
TPS628680ARQYR from Texas Instruments is a 4-A synchronous step-down DC/DC converter with I²C interface, DCS-Control™ topology, and 2.4-MHz fixed-frequency PWM operation. It delivers 0.2-V to 0.8375-V output with 2.5-mV step resolution, 1% voltage accuracy, and >90% efficiency at 0.9-V output-designed for LPDDR5 VDDQ rail supply in space-constrained mobile SoC applications.
For engineers reviewing the TPS628680ARQYR datasheet, TPS628680ARQYR pinout, TPS628680ARQYR application, or TPS628680ARQYR equivalent, key selection considerations include its 9-pin QFN (1.5 × 2.5 mm) package, I²C-configurable power-save/forced-PWM modes, thermal pre-warning capability, and start-up output voltage selectability via external resistor on VSET/VID.
Technical Context
The TPS628680ARQYR implements DCS-Control™ architecture to unify PWM and Power Save Mode (PSM) operation within a single control loop-enabling seamless transition between 2.4-MHz fixed-frequency regulation and variable-frequency PSM without output voltage disturbance. Its dual internal MOSFETs (11-mΩ HS / 10.5-mΩ LS) support high-efficiency conversion across 2.4–5.5-V input range while maintaining tight transient response.
Output voltage is dynamically scalable via I²C across three discrete ranges (0.2–0.8375 V, 0.4–1.675 V, 0.8–3.35 V), with this variant locked to the 0.2–0.8375-V range and 2.5-mV steps. Start-up voltage is user-selectable (0.2–0.575 V) using an external resistor on VSET/VID, and the pin repurposes post-startup for register bank selection (VOUT1/VOUT2).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.4 V to 5.5 V - supports single-cell Li-ion, USB PD, and intermediate bus rails without external LDO pre-regulation. |
| Output Current | 4 A continuous - rated for sustained operation up to 125°C junction temperature with appropriate PCB thermal design. |
| Output Voltage Range | 0.2 V to 0.8375 V in 2.5-mV steps - optimized for low-voltage core rails including LPDDR5 VDDQ and FPGA I/O banks. |
| Switching Frequency | 2.4 MHz nominal - enables use of ultra-small 0.22-µH inductors and reduces EMI filtering burden in compact layouts. |
| Efficiency | >90% at 0.9-V output - achieved via low RDS(on) FETs (11 mΩ HS / 10.5 mΩ LS) and adaptive DCS-Control™ modulation. |
| Output Accuracy | ±1% over temperature and load - ensures stable voltage margining for advanced memory interfaces requiring tight VDDQ tolerance. |
| I²C Interface Speed | Up to 3.4 Mbps (high-speed mode) - supports rapid dynamic voltage scaling during CPU/FPGA performance state transitions. |
Pinout & Package
TPS628680ARQYR is housed in a thermally enhanced 9-pin QFN package (RQY) measuring 1.5 mm × 2.5 mm × 1.0 mm with 0.5-mm pitch and wettable flanks for automated optical inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 AGND | Analog ground reference | Low-noise return path for feedback and control circuitry; must be connected to quiet analog ground plane. |
| 2 PGND | Power ground return | High-current return for switch node and output capacitor; requires low-inductance connection to thermal pad. |
| 3 VIN | Main input power supply | Accepts 2.4–5.5 V; requires local 10-µF ceramic input capacitor placed adjacent to pin. |
| 4 EN | Enable control input | Active-high logic input; internal pull-down ensures safe default-off state; must not be left floating. |
| 5 SDA | I²C serial data line | Open-drain bidirectional interface; requires external pull-up to system I²C bus voltage (≤5.5 V). |
| 6 SCL | I²C serial clock line | Input-only clock signal; supports standard/fast/fast-plus/high-speed I²C modes up to 3.4 Mbps. |
| 7 SW | Switch node | Connects to external inductor; high dv/dt node requiring minimized trace area and separation from sensitive signals. |
| 8 VOS | Output voltage sense | Direct Kelvin connection point to output capacitor; critical for ±1% accuracy-must avoid routing under IC body. |
| 9 VSET/VID | Start-up voltage & register select | Resistor-programmable start-up voltage (0.2–0.575 V); toggles between VOUT registers after startup for dual-rail DVS. |
Key Features
| Feature | Design Value |
|---|---|
| DCS-Control™ topology | Unifies PWM and PSM operation in one control loop-eliminates mode-transition artifacts and maintains <10-mV load transient deviation at 4-A step. |
| I²C-configurable protection | Selectable hiccup or latching short-circuit response, output discharge enable/disable, and forced PWM mode-all programmable without hardware change. |
| Thermal pre-warning | Dedicated TJW = 130°C threshold triggers interrupt flag via I²C before thermal shutdown (150°C), enabling proactive thermal management in SoC systems. |
| Voltage ramp control | Programmable soft-start ramp speed (via I²C) prevents inrush current into pre-biased outputs-critical for hot-plug and multi-rail sequencing. |
| Power-good window comparator | Configurable upper/lower thresholds (91–120% of VOUT) with 34-µs deglitch-ensures reliable system reset assertion for memory and processor rails. |
Applications
| LPDDR5 Memory Supply | FPGA Core Rail |
|---|---|
Use Scenario: Provides VDDQ supply for LPDDR5 DRAM in mobile and edge AI accelerators where voltage must scale dynamically with bandwidth demand. IC Role / Device Role / Timing Role: Primary buck regulator with I²C-controlled DVS, delivering 0.2–0.8375 V at up to 4 A with <1% accuracy and sub-1-ms ramp time. Use Value: Enables real-time VDDQ scaling to reduce active power by up to 30% versus fixed-voltage solutions, while maintaining JEDEC timing margins. |
Use Scenario: Powers configurable logic fabric and I/O banks in Xilinx Versal or Intel Agilex FPGAs during partial reconfiguration and thermal throttling events. IC Role / Device Role / Timing Role: High-density, thermally robust step-down converter with thermal pre-warning and programmable soft-start for safe rail sequencing. Use Value: Supports FPGA dynamic power management via I²C register writes-no external PMIC required-reducing BOM count and board area by 40%. |
| Solid-State Drive Controller | IP Network Camera SoC |
Use Scenario: Supplies NVMe controller core voltage in M.2 SSDs where burst workloads cause rapid current transients and thermal spikes. IC Role / Device Role / Timing Role: 4-A buck with DCS-Control™ and 2.4-MHz switching-delivers <50-ns response to 2-A load steps while maintaining <15-mV undershoot. Use Value: Eliminates need for large bulk capacitance; enables 1210-size 0.22-µH inductor and total solution size <25 mm². |
Use Scenario: Powers image signal processor (ISP) and video encoder cores in 4K IP cameras operating in wide ambient temperature ranges (-40°C to +85°C). IC Role / Device Role / Timing Role: I²C-managed power rail with thermal pre-warning and shutdown (130°C/150°C) to prevent ISP lockup during extended recording. Use Value: Maintains stable 0.6-V core supply under 100% CPU utilization-verified across 10k thermal cycles without derating. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS628690ARQYR | 6-A rating, identical package and I²C feature set; higher current limit (7–8.5 A) and lower RDS(on) (10.5/9.5 mΩ). | Required for designs needing >4-A peak current or tighter thermal headroom at full load. | Select when future-proofing for higher-power SoCs or when operating near thermal limits with 4-A TPS628680ARQYR. |
| TPS62903RQYR | 3-A, 2.5-V to 5.5-V input, 1.8-MHz switching, no I²C-uses resistor-based VOUT setting and fixed PFM/PWM mode selection. | Lacks dynamic voltage scaling and thermal warning; suited for cost-sensitive, static-voltage applications. | Choose for simpler, lower-BOM-cost designs where I²C control and DVS are unnecessary-e.g., fixed-function peripherals. |
Compared with TPS628690ARQYR and TPS62903RQYR, the TPS628680ARQYR uniquely balances 4-A capability, ultra-low 0.2-V minimum output, and full I²C configurability in a 1.5 × 2.5-mm footprint-making it optimal for LPDDR5 VDDQ and FPGA I/O rails where voltage agility and space are constrained.
Availability
TPS628680ARQYR is available at Aetrix Electronics and suitable for LPDDR5 memory supply, FPGA core rail, solid-state drive controller, and IP network camera SoC applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for TPS628680ARQYR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies-with over 50 years of innovation in high-efficiency DC/DC conversion.
The TPS62868x family was designed specifically for next-generation mobile and AI edge processors requiring ultra-low-voltage, high-current, and digitally controllable power rails-targeting LPDDR5, PCIe Gen5, and heterogeneous SoC architectures.
FAQ
What is the minimum output voltage supported by the TPS628680ARQYR?
The TPS628680ARQYR supports a minimum output voltage of 0.2 V with 2.5-mV step resolution across its full 0.2-V to 0.8375-V range. This is confirmed in the Device Options table and Electrical Characteristics section of the official datasheet (SLVSFS3B), where TPS628680ARQYR is explicitly designated for the 0.2–0.8375-V DVS range. The 0.2-V floor enables direct powering of LPDDR5 VDDQ rails without external level-shifting.
Does the TPS628680ARQYR support forced PWM mode, and how is it enabled?
Yes, the TPS628680ARQYR supports forced PWM (FPWM) mode to eliminate low-frequency ripple and ensure constant 2.4-MHz switching regardless of load. FPWM is enabled via bit 0 (FPWM_EN) in the CONTROL register (address 0x01) using the I²C interface. When activated, the device maintains PWM operation down to zero load, improving EMI predictability but reducing light-load efficiency compared to Power Save Mode.
What is the function of the VSET/VID pin on the TPS628680ARQYR after power-up?
After power-up and completion of the enable delay (~700 µs), the VSET/VID pin on the TPS628680ARQYR functions as a register bank selector: logic low selects VOUT register 1 (primary DVS voltage), and logic high selects VOUT register 2 (secondary DVS voltage). This allows rapid switching between two preconfigured output voltages via GPIO toggle-complementing I²C-based fine-grained adjustment.
Can the TPS628680ARQYR start into a pre-biased output capacitor?
Yes, the TPS628680ARQYR supports pre-biased start-up. As documented in Section 8.3.4 of the datasheet, the device detects the existing output voltage and ramps from that bias point to the target VOUT-preventing reverse current flow and ensuring safe hot-insertion into live systems such as modular SSDs or field-upgradable camera modules.
What thermal protection features does the TPS628680ARQYR provide?
The TPS628680ARQYR provides dual thermal protection: a thermal pre-warning flag (TJW = 130°C) that asserts via I²C status register to trigger firmware thermal throttling, and hard thermal shutdown (TJSD = 150°C) with 20°C hysteresis. Both thresholds are silicon-characterized and do not require external components-enabling robust operation in sealed enclosures like IP67-rated cameras or automotive infotainment units.
TPS628680ARQYR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 9-PowerVFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.4V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.2V
- Voltage - Output (Max):
- 0.8375V
- Current - Output:
- 4A
- Frequency - Switching:
- 2.4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 9-VQFN-HR (1.5x2.5)
TPS628680ARQYR FAQ
1.How can I place an order for TPS628680ARQYR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS628680ARQYR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS628680ARQYR reliable?
The price and inventory of TPS628680ARQYR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS628680ARQYR is usually 5 days.
3.What payment methods are accepted for TPS628680ARQYR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS628680ARQYR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS628680ARQYR?
TPS628680ARQYR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS628680ARQYR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS628680ARQYR?
For technical support, including TPS628680ARQYR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS628680ARQYR requirements.
6.How does Aetrix verify that TPS628680ARQYR is sourced from the original manufacturer or authorized distributors?
All TPS628680ARQYR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS628680ARQYR meets industry standards.
7.What is the process for return or replacement of TPS628680ARQYR?
All TPS628680ARQYR units undergo pre-shipment inspection (PSI). If there is an issue with TPS628680ARQYR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS628680ARQYR part is unused and in its original packaging.
Return procedure for TPS628680ARQYR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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