Texas Instruments TPS628681ARQYR
- Part No.:
- TPS628681ARQYR
- Manufacturer:
- Texas Instruments
- Package:
- 9-PowerVFQFN
- Datasheet:
-
TPS628681ARQYR.pdf
- Description:
- IC REG BUCK PROG 4A 9VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:5,502
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
TPS628681ARQYR from Texas Instruments is a 4-A synchronous step-down DC/DC converter with I²C interface, designed for dynamic voltage scaling in high-performance digital loads. It operates from 2.4 V to 5.5 V input, delivers 0.4 V to 1.675 V output with 5-mV step resolution, achieves >90% efficiency at 0.9-V output, and uses DCS-Control™ topology for sub-10-µs load transient response - deployed in LPDDR5 VDDQ rail supply and FPGA core power.
For engineers reviewing the TPS628681ARQYR datasheet, TPS628681ARQYR pinout, TPS628681ARQYR application, or TPS628681ARQYR equivalent, key selection criteria include I²C-configurable DVS ranges, 2.4-MHz fixed-frequency PWM mode, thermal pre-warning capability, 1% output voltage accuracy, and QFN-9 (1.5 × 2.5 mm) package compatibility with space-constrained embedded power designs.
Technical Context
The TPS628681ARQYR integrates dual MOSFETs (11-mΩ HS / 10.5-mΩ LS) and employs DCS-Control™ architecture to unify PWM and Power Save Mode operation without output disturbance. Its I²C interface supports up to 3.4 Mbps, enabling real-time register access for output discharge control, hiccup/latching short-circuit protection selection, and programmable ramp speed.
Startup output voltage is resistor-selectable between 0.4 V and 1.15 V via the VSET/VID pin, and the device features dedicated VOS sensing for ±1% output accuracy across –40°C to 125°C. Thermal warning triggers at 130°C with 20°C hysteresis, preceding 150°C shutdown.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.4 V to 5.5 V - supports single-cell Li-ion, USB PD, and industrial 3.3-V/5-V rails. |
| Output Current | 4 A continuous - rated for sustained operation up to 105°C junction temperature. |
| Output Voltage Range | 0.4 V to 1.675 V with 5-mV steps - enables precise DVS for LPDDR5 VDDQ and CPU cores. |
| Switching Frequency | 2.4 MHz fixed - allows use of ultra-small 0.22-µH inductors and minimizes EMI filtering area. |
| Efficiency | >90% at 0.9-V output - reduces thermal load in dense SoC/FPGA power delivery networks. |
| Output Accuracy | ±1% - ensures stable logic rail compliance under full load, line, and temperature variation. |
| I²C Speed | Up to 3.4 Mbps (high-speed mode) - enables fast VID updates during performance state transitions. |
Pinout & Package
TPS628681ARQYR is housed in a thermally enhanced 9-pin QFN package (RQY), measuring 1.5 mm × 2.5 mm × 1.0 mm with 0.5-mm pitch and wettable flanks for automated optical inspection. The exposed thermal pad (Pin 2, PGND) must be soldered to PCB ground for optimal thermal performance (RθJA = 90.9°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AGND (Pin 1) | Analog reference ground | Separate low-noise return path for feedback and I²C circuitry; must connect to quiet analog ground plane. |
| PGND (Pin 2) | Power ground | High-current return for SW node and internal FETs; ties directly to thermal pad and bulk output capacitor ground. |
| VIN (Pin 3) | Main input supply | Accepts 2.4–5.5 V; requires local 10-µF ceramic input capacitor placed adjacent to Pin 3 and PGND. |
| EN (Pin 4) | Enable control | Active-high logic input; 0.4 V low threshold and 0.84 V high threshold enable direct MCU GPIO drive. |
| SDA (Pin 5) | I²C data line | Open-drain, supports 3.4 Mbps high-speed mode; requires external pullup to 1.8–5.5 V. |
| SCL (Pin 6) | I²C clock line | Open-drain, synchronized with SDA; same pullup requirements and noise immunity design as SDA. |
| SW (Pin 7) | Switch node | Connects to inductor; carries high di/dt switching current - requires tight loop routing with minimal trace length. |
| VOS (Pin 8) | Output voltage sense | Direct Kelvin connection point to output capacitor - critical for ±1% regulation accuracy. |
| VSET/VID (Pin 9) | Startup voltage & address select | Resistor-programmable start-up voltage (0.4–1.15 V); after startup, selects between two I²C VOUT registers. |
Key Features
| Feature | Design Value |
|---|---|
| DCS-Control™ topology | Enables seamless PWM-to-PSM transition with <10 µs load transient recovery and no output voltage glitch. |
| I²C-configurable protection | Selectable hiccup or latching short-circuit response, plus programmable output discharge timing. |
| Thermal pre-warning | Dedicated flag at 130°C alerts host controller before thermal shutdown at 150°C - enables proactive throttling. |
| VOS Kelvin sensing | Eliminates IR drop error from PCB traces, maintaining ±1% output accuracy even with 100-mΩ board resistance. |
| Forced PWM mode | Disables PSM via I²C to sustain 2.4-MHz switching at light load - reduces output ripple for noise-sensitive analog circuits. |
Applications
| LPDDR5 Memory Supply | FPGA Core Power |
|---|---|
Use Scenario: Providing tightly regulated VDDQ rail for LPDDR5 DRAM in mobile and edge AI accelerators. IC Role / Device Role / Timing Role: Primary buck regulator delivering dynamically scaled 0.6–1.1 V at up to 4 A with I²C-synchronized voltage transitions. Use Value: 5-mV DVS steps and 1% accuracy ensure JEDEC-compliant VDDQ margining while minimizing power waste during low-bandwidth states. | Use Scenario: Powering heterogeneous FPGA fabric and hardened processor blocks requiring rapid voltage adaptation. IC Role / Device Role / Timing Role: High-density step-down converter with 2.4-MHz switching and DCS-Control™ for sub-5-µs load step recovery. Use Value: Enables real-time DVFS in response to compute workload changes - reducing average system power by up to 22% versus fixed-voltage solutions. |
| IP Network Camera SoC | Solid-State Drive Controller |
Use Scenario: Supplying core voltage to image signal processors (ISP) and video encoders in compact IP cameras. IC Role / Device Role / Timing Role: Compact 1.5 × 2.5 mm buck converter supporting 0.4–1.675 V output range and thermal pre-warning for fanless enclosures. Use Value: Small QFN package and integrated MOSFETs eliminate external FET layout complexity while maintaining 90%+ efficiency at 1-A typical load. | Use Scenario: Delivering stable 1.2-V or 1.8-V rails to NAND flash controllers and PCIe Gen4 PHYs in M.2 SSDs. IC Role / Device Role / Timing Role: I²C-programmable buck regulator with hiccup-mode short-circuit protection and VOS-sense accuracy. Use Value: Prevents catastrophic failure during NAND hot-plug events and maintains strict voltage tolerance (<±2%) during burst write operations. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous step-down converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS628680ARQYR | Lower output range (0.2–0.8375 V, 2.5-mV steps), 4-A rating, same package and I²C interface. | Optimized for sub-0.6-V logic rails (e.g., advanced CPU cores), not LPDDR5 VDDQ or FPGA I/O banks. | Select when target output is ≤0.8375 V and finer 2.5-mV DVS resolution is required. |
| TPS628691ARQYR | 6-A output capability, identical 0.4–1.675 V DVS range and 5-mV steps, same QFN-9 package. | Supports higher-current SoCs (e.g., multi-core AI processors) where 4-A headroom is insufficient. | Choose when peak load exceeds 4 A but same DVS profile and footprint compatibility are mandatory. |
Compared with TPS628680ARQYR, TPS628681ARQYR provides higher minimum output (0.4 V vs. 0.2 V) and coarser DVS steps - better matching LPDDR5 VDDQ specifications. Against TPS628691ARQYR, it trades 2-A output headroom for lower quiescent current and optimized thermal behavior at 4-A continuous load.
Availability
TPS628681ARQYR is available at Aetrix Electronics and suitable for LPDDR5 memory supplies, FPGA core power systems, and IP network camera SoC designs requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for TPS628681ARQYR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs, with decades of expertise in high-efficiency DC/DC conversion.
The TPS62868x family was developed specifically for dynamic voltage scaling in next-generation memory interfaces and programmable logic devices - emphasizing ultra-small footprint, I²C configurability, and precision regulation under fast transients.
FAQ
What is the maximum supported I²C clock frequency for TPS628681ARQYR?
The TPS628681ARQYR supports I²C high-speed mode up to 3.4 Mbps for both read and write operations when bus capacitance is ≤100 pF. At 400-pF bus load, maximum clock frequency drops to 1.7 Mbps. All timing parameters - including tLOW, tHIGH, and tSU, tDAT - are fully specified in Section 7.6 of the datasheet and remain compliant across –40°C to 125°C junction temperature.
Does TPS628681ARQYR support power-good monitoring with window comparator functionality?
Yes, TPS628681ARQYR includes a power-good (PG) indicator with window comparator functionality when configured with the VSET/VID pin assigned to PG mode. However, the TPS628681ARQYR variant uses VSET/VID for startup voltage selection and register addressing - so PG functionality is not enabled by default. To use PG, a different variant such as TPS6286810CRQYR must be selected.
What is the recommended inductor value for TPS628681ARQYR in a typical 1.2-V output design?
For the TPS628681ARQYR operating with 1.2-V output and 5-V input, Texas Instruments specifies a 220-nH shielded power inductor (e.g., Coilcraft XAL5030-221MEB or equivalent). This value balances peak inductor current, ripple magnitude (~240 mA), and transient response - and is validated in the device's typical application circuit (Figure 9-2). Lower values increase ripple; higher values degrade transient performance.
Can TPS628681ARQYR start into a pre-biased output capacitor?
Yes, TPS628681ARQYR supports pre-biased start-up. When enabled, the device detects the existing output voltage and ramps from that bias level to the target VOUT using its internal soft-start circuitry (tRamp = 0.85–1.5 ms). This prevents reverse current flow into the output capacitor and avoids disruptive voltage undershoot - critical in hot-swap and multi-rail sequencing applications.
How does thermal pre-warning work on TPS628681ARQYR, and how is it signaled?
TPS628681ARQYR monitors die temperature internally and asserts thermal pre-warning at 130°C (with 20°C hysteresis). Unlike thermal shutdown, this flag is not a pin-level signal - it is accessible only via I²C register read (STATUS register bit [THERM_WARN]). Host firmware can poll this bit to initiate cooling actions or performance throttling before reaching 150°C shutdown.
TPS628681ARQYR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 9-PowerVFQFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Programmable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.4V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.4V
- Voltage - Output (Max):
- 1.675V
- Current - Output:
- 4A
- Frequency - Switching:
- 2.4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 9-VQFN-HR (1.5x2.5)
TPS628681ARQYR FAQ
1.How can I place an order for TPS628681ARQYR through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS628681ARQYR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS628681ARQYR reliable?
The price and inventory of TPS628681ARQYR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS628681ARQYR is usually 5 days.
3.What payment methods are accepted for TPS628681ARQYR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for TPS628681ARQYR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS628681ARQYR?
TPS628681ARQYR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS628681ARQYR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS628681ARQYR?
For technical support, including TPS628681ARQYR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS628681ARQYR requirements.
6.How does Aetrix verify that TPS628681ARQYR is sourced from the original manufacturer or authorized distributors?
All TPS628681ARQYR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS628681ARQYR meets industry standards.
7.What is the process for return or replacement of TPS628681ARQYR?
All TPS628681ARQYR units undergo pre-shipment inspection (PSI). If there is an issue with TPS628681ARQYR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS628681ARQYR part is unused and in its original packaging.
Return procedure for TPS628681ARQYR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
TPS628681ARQYR Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
