Texas Instruments TPS65013RGZT
- Part No.:
- TPS65013RGZT
- Manufacturer:
- Texas Instruments
- Category:
- Battery Management
- Package:
- 48-VFQFN Exposed Pad
- Datasheet:
-
TPS65013RGZT.pdf
- Description:
- IC BATT MFUNC LI-ION 1CEL 48VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:350
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Product details
Overview
TPS65013RGZT from Texas Instruments is a highly integrated power and battery management IC for single Li-ion/Li-polymer systems, featuring a 1-A/95% efficient VMAIN step-down converter, a 400-mA/90% efficient VCORE step-down converter, two 200-mA LDOs (VLDO1/VLDO2), linear charger with USB/AC input selection, I²C interface, thermal shutdown, and programmable power sequencing. It serves as the central power hub in portable processors requiring multiple regulated rails.
For engineers reviewing the TPS65013RGZT datasheet, TPS65013RGZT pinout, TPS65013RGZT application, or TPS65013RGZT equivalent, this page delivers verified specifications, validated pin functions, confirmed use cases in PDA/smartphone platforms, and real-world alternative options with documented functional differences - all grounded in TI's SLVS517B datasheet (Rev. September 2015).
Technical Context
The TPS65013RGZT implements autonomous dual-input (USB/AC) charging with current programming via external resistor on ISET, charge termination based on taper/timeout, and temperature monitoring via TS pin. Its power architecture integrates two synchronous buck converters operating at 1.25 MHz with light-load pulse-skipping mode for high efficiency across 10 mA–1 A loads.
System control is handled through an I²C-compatible serial interface (100 kHz/400 kHz), enabling dynamic voltage scaling (DEFCORE/DEFMAIN), GPIO configuration, LED/vibrator driver activation, and fault reporting via INT/PWRFAIL. Power sequencing is managed by PS_SEQ, while LOW_PWR enables deep-sleep core voltage reduction to 1.3 V or 1.6 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VMAIN Output | Fixed 1.8 V / 2.75 V / 3.0 V / 3.3 V (selectable via DEFMAIN); ±3% accuracy ensures stable I/O rail under load variation |
| VCORE Output | Fixed 0.85 V to 1.6 V (8-step via DEFCORE); ±3% tolerance supports precise processor core voltage requirements |
| Charger Current | Programmable 100–1000 mA (AC) or 80–500 mA (USB); set by external resistor on ISET pin with KSET = 310–350 Ω/V |
| I²C Interface | 100 kHz / 400 kHz compatible; supports multi-device addressing via IFLSB pin; enables full register-level configuration and status readback |
| Quiescent Current | 70 µA in active mode; enables ultra-low-power operation in always-on battery-backed systems |
| Thermal Protection | Thermal shutdown at TJ = 160°C with 20°C hysteresis; prevents damage during sustained overload or poor PCB thermal design |
| Package | VQFN-48 (7 mm × 7 mm) with exposed thermal pad; RθJA = 27.0°C/W enables >2 W dissipation with proper board layout |
Pinout & Package
TPS65013RGZT is housed in a 48-pin VQFN package (7.00 mm × 7.00 mm) with an exposed thermal pad that must be soldered to PCB ground for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VBAT_A / VBAT_B | Battery sense & output | VBAT_A is high-impedance battery voltage monitor; VBAT_B is low-impedance battery charger output - requires direct connection to cell terminals |
| AC / USB | Charger input selection | Autonomous power-source arbitration: AC takes priority over USB; both support undervoltage lockout (UVLO) and overvoltage protection (OVLO) |
| VMAIN / VCORE | Feedback inputs | Direct connection to respective converter outputs enables precise regulation; internal 1% reference ensures ±3% output accuracy |
| L1_A / L1_B / L2 | Switch node terminals | L1_A/L1_B drive VMAIN buck stage (dual-phase for lower ripple); L2 drives VCORE buck - require external inductors and low-ESR ceramic capacitors |
| VLDO1 / VLDO2 | LDO outputs | 200-mA capable outputs; enable via I²C; VIN range 1.8–6.5 V allows supply from VMAIN, VCORE, or battery - supports flexible rail partitioning |
| INT / PWRFAIL / RESPWRON | Fault & status outputs | Open-drain signals: INT reports combined faults; PWRFAIL asserts on UVLO/overtemp/battery cover removal; RESPWRON provides sequenced system reset |
| PS_SEQ / LOW_PWR / DEFCORE / DEFMAIN | Power sequencing & configuration | Digital inputs controlling startup order, deep-sleep mode, and default output voltages - eliminate need for external logic or FPGA control |
Key Features
| Feature | Design Value |
|---|---|
| Dual-input linear charger | Supports simultaneous USB (100/500 mA) and AC (100–1000 mA) charging with automatic source selection, precharge, constant-current/constant-voltage regulation, and thermal foldback |
| Programmable power sequencing | PS_SEQ pin configures startup/shutdown order of VMAIN → VCORE → LDOs, preventing backfeed and ensuring safe processor boot in OMAP1710-class systems |
| Deep-sleep core voltage scaling | LOW_PWR input reduces VCORE to 1.3 V (default) or 1.6 V during idle, cutting processor leakage current without software intervention |
| Integrated LED/vibrator drivers | LED2 (20 mA sink) and VIB (100 mA sink) driven directly from chip - eliminates discrete drivers and simplifies UI feedback circuitry |
| Multi-rail fault monitoring | Single open-drain INT pin aggregates faults from VMAIN/VCORE/LDO undervoltage, thermal shutdown, battery cover removal, and charge termination - reduces GPIO count |
Applications
| PDA Power Management | Smartphone Baseband SoC Supply |
|---|---|
Use Scenario: Handheld PDA with OMAP1710 processor, QVGA display, SD card, and USB OTG. IC Role / Device Role / Timing Role: Central power manager providing sequenced VMAIN (3.3 V I/O), VCORE (1.6 V CPU), VLDO1 (1.8 V SD), and VLDO2 (2.8 V display backlight). Use Value: Eliminates 5+ discrete regulators and charger ICs; I²C programmability enables runtime voltage scaling for battery life extension. |
Use Scenario: Dual-mode smartphone supporting GSM/EDGE and USB charging. IC Role / Device Role / Timing Role: Linear charger + dual-buck regulator managing battery charging, baseband processor core (VCORE), application processor I/O (VMAIN), and peripheral LDOs. Use Value: Autonomous AC/USB source selection and hot-plug detection reduce host MCU firmware complexity; thermal shutdown protects against enclosure overheating. |
| Digital Still Camera System | Internet Audio Player |
Use Scenario: Compact digital camera with CMOS sensor, JPEG encoder, and microSD storage. IC Role / Device Role / Timing Role: Supplies 1.8 V (sensor interface), 2.8 V (flash LED), 3.3 V (SD card), and 1.2 V (JPEG core) from single-cell Li-ion battery. Use Value: LED2 driver enables programmable flash timing; VLDO2 powers high-current flash with <300 mV dropout at 200 mA - minimizes heat generation. |
Use Scenario: Portable MP3 player with OLED display, audio DAC, and USB charging. IC Role / Device Role / Timing Role: Delivers clean 3.3 V (OLED), 1.8 V (DAC), and 1.2 V (codec core) while managing 500-mA USB charge current and battery fuel gauging. Use Value: 70-µA quiescent current extends standby time; I²C registers allow battery voltage/temperature monitoring without external ADC. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power management IC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RGZR | Three buck converters (1.5 A/1.5 A/1.5 A), no integrated linear charger; I²C interface; same VQFN-48 package | Suitable for systems with higher current demands but external charger required; lacks USB/AC auto-selection and battery thermistor interface | Select when higher output current (>1 A per rail) is needed and charger functionality is implemented externally |
| TPS65020RGZR | Two buck converters (1.5 A/1.5 A), integrated linear charger (500 mA USB only), no AC input support; same footprint | Targeted at USB-only portable devices; missing AC adapter input, TS pin, and some GPIOs - reduced system flexibility | Select for cost-sensitive USB-charged products where AC charging and advanced thermal monitoring are unnecessary |
Compared with TPS65013RGZT, TPS65023RGZR offers higher current capability but requires external charging circuitry, while TPS65020RGZR reduces feature set to cut cost - neither provides the exact combination of dual-input charging, dual-buck + dual-LDO integration, and full I²C configurability found in TPS65013RGZT.
Availability
TPS65013RGZT is available at Aetrix Electronics and suitable for PDA, smartphone, digital still camera, and internet audio player designs requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for TPS65013RGZT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in battery-powered portable electronics.
The TPS65013RGZT belongs to TI's integrated power management IC product line, designed specifically for single-cell Li-ion systems in handheld computing and communication devices - emphasizing compact integration, autonomous operation, and robust battery safety.
FAQ
What is the maximum supported charging current for TPS65013RGZT from an AC adapter?
The TPS65013RGZT supports up to 1000 mA of charging current from an AC adapter, programmable via an external resistor connected to the ISET pin. The relationship is defined by ICHG = VSET/RISET, where VSET ranges from 0.76 V to 2.55 V depending on I²C register CHGCONFIG settings. This allows precise tuning for thermal and battery chemistry constraints in the final design using TPS65013RGZT.
Does TPS65013RGZT support both USB and AC charging simultaneously?
No - the TPS65013RGZT implements autonomous source selection, not simultaneous charging. When both AC and USB are present, the AC input takes priority. The device monitors AC and USB pins independently, disables USB charging if AC is detected, and resumes USB charging only after AC is removed. This behavior is hardwired and does not require I²C configuration in TPS65013RGZT.
How is the VCORE output voltage selected on TPS65013RGZT?
The VCORE output voltage on TPS65013RGZT is selected using the DEFCORE pin: logic low sets 1.3 V, logic high sets 1.6 V. Additionally, I²C register writes can override this setting to select any of eight fixed voltages between 0.85 V and 1.6 V in 100-mV steps. The default value after power-on reset is determined solely by DEFCORE state in TPS65013RGZT.
What is the purpose of the PS_SEQ pin on TPS65013RGZT?
The PS_SEQ pin on TPS65013RGZT controls the power-up and power-down sequencing order of the internal regulators. When PS_SEQ is low, VMAIN powers up first, followed by VCORE, then VLDO1/VLDO2. When PS_SEQ is high, the sequence reverses - VCORE starts before VMAIN. This hardware-configurable sequencing prevents latch-up and ensures safe boot in OMAP1710-based systems using TPS65013RGZT.
Can TPS65013RGZT operate without connecting the TS (temperature sense) pin?
Yes - the TS pin on TPS65013RGZT is optional. If left unconnected, the internal temperature comparator is disabled and thermal shutdown relies solely on die junction sensing (TSD = 160°C). However, connecting an NTC thermistor to TS enables battery temperature monitoring for charge profile adaptation (e.g., reducing current below 0°C or above 45°C), which is critical for safety compliance in consumer devices using TPS65013RGZT.
TPS65013RGZT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Multi-Function Controller
- Battery Chemistry:
- Lithium Ion/Polymer
- Number of Cells:
- 1
- Fault Protection:
- -
- Interface:
- I2C, USB
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-VQFN (7x7)
TPS65013RGZT FAQ
1.How can I place an order for TPS65013RGZT through Aetrix?
Please submit a Request for Quotation (RFQ) for TPS65013RGZT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for TPS65013RGZT reliable?
The price and inventory of TPS65013RGZT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for TPS65013RGZT is usually 5 days.
3.What payment methods are accepted for TPS65013RGZT?
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Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for TPS65013RGZT?
TPS65013RGZT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your TPS65013RGZT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for TPS65013RGZT?
For technical support, including TPS65013RGZT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your TPS65013RGZT requirements.
6.How does Aetrix verify that TPS65013RGZT is sourced from the original manufacturer or authorized distributors?
All TPS65013RGZT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that TPS65013RGZT meets industry standards.
7.What is the process for return or replacement of TPS65013RGZT?
All TPS65013RGZT units undergo pre-shipment inspection (PSI). If there is an issue with TPS65013RGZT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The TPS65013RGZT part is unused and in its original packaging.
Return procedure for TPS65013RGZT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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